• 한국정보통신학회논문지
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• 제10권2호
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• pp.328-332
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• 2006

정보 보호 응용에 새로운 이슈가 되고 있는 ECC 공개키 암호 알고리즘은 유한체 차원에서의 효율적인 연산처리가 중요하다. 직렬 유한체 곱셈기의 근간은 Mastrovito의 직렬 곱셈기에서 유래한다. 본 논문에서는 polynomial basis 방식을 적용하고 식을 유도하여 Mastrovito의 직렬 유한체 곱셈방식의 3배 성능을 보이는 유한체 곱셈기를 제안하고, HDL로 기술하여 기능을 검증하고 성능을 평가한다. 설계된 3배속 직렬 유한체 곱셈기는 부분합을 생성하는 회로의 추가만으로 기존 직렬 곱셈기의 3배의 성능을 보여주었다. 비도 높은 암호용으로 연구된 유한체 곱셈 연산기는 크게 직렬 유한체 곱셈기, 배열 유한체 곱셈기, 하이브리드 유한체 곱셈기으로 분류되어 왔다. 본 논문에서는 Mastrovito의 곱셈기의 구조를 기본으로 하고, 수식적으로 공통인수를 끌어내어 후처리하는 기법을 유도하여 적용한다. 제안한 방식으로 설계한 새로운 유한체 곱셈기는 HDL로 구현하여 소프트웨어 측면 뿐 아니라 하드웨어 측면에서도 그 기능과 성능을 검증하였다.

• ETRI Journal
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• 제27권5호
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• pp.511-524
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• 2005

In this paper, we propose a novel hardware architecture for an intra-prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quantization/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing $4{\times}4$ Hadamard transform and quantization during $16{\times}16$ prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix $0.35 {\mu}m$ TLM (triple layer metal) library.

• 한국컴퓨터그래픽스학회논문지
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• 제2권1호
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• pp.15-23
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• 1996

범프 맵핑(bump mapping)은 나무껍질과 같은 울퉁불퉁한 물체를 표현하기 위한 방법으로서 텍스쳐 맵핑(texture mapping)보다 더욱 사실적인 영상을 얻을 수 있는 렌더링(rendering) 기법이다. 본 논문에서는 기존의 범프 맵핑 알고리즘의 단점을 보완한 새로운 알고리즘을 제시하며, 또한 이 알고리즘을 실시간으로 처리하기 위한 하드웨어 구조를 제시한다. 이는 기존의 구조에 비해 구현하기가 더욱 간단한 것이다.

• 한국통신학회논문지
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• 제41권11호
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• pp.1502-1506
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• 2016

HEVC (High Efficiency Video Coding)는 최근에 제안된 비디오 압축 표준으로서 이전의 비디오 압축 표준보다 두 배 이상의 부호화 효율을 가진다. 다양한 종류의 인트라 예측 블록과 모드는 HEVC의 높은 압축 성능과 연산 복잡도 증가의 주요 요인이다. 본 논문은 파이프라인과 인터리빙 기술을 사용하여 하드웨어 자원의 요구조건을 줄이는 반면 효율과 성능은 향상시킨 HEVC 용 인트라 예측 하드웨어 구조를 제시한다.

• ETRI Journal
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• 제30권5호
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• pp.707-717
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• 2008

This paper presents two types of high-speed hardware architectures for the block cipher ARIA. First, the loop architectures for feedback modes are presented. Area-throughput trade-offs are evaluated depending on the S-box implementation by using look-up tables or combinational logic which involves composite field arithmetic. The sub-pipelined architectures for non-feedback modes are also described. With loop unrolling, inner and outer round pipelining techniques, and S-box implementation using composite field arithmetic over $GF(2^4)^2$, throughputs of 16 Gbps to 43 Gbps are achievable in a 0.25 ${\mu}m$ CMOS technology. This is the first sub-pipelined architecture of ARIA for high throughput to date.

• ETRI Journal
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• 제28권4호
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• pp.525-528
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• 2006

In this letter, we present a design of a single chip video decoder called advanced mobile video ASIC (A-MoVa) for mobile multimedia applications. This chip uses a mixed hardware/software architecture to improve both its performance and its flexibility. We designed the chip using a partition between the hardware and software blocks, and developed the architecture of an H.264 decoder based on the system-on-a-chip (SoC) platform. This chip contains 290,000 logic gates, 670,000 memory gates, and its size is $7.5\;mm{\times}7.5\;mm$ (using 0.25 micron 4-layers metal CMOS technology).

• 전자공학회논문지A
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• 제33A권10호
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• pp.168-176
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• 1996

This paper presetns a 2-D DCT architecture adopting accurac y compensator for reducing the hardware complexity and increasing processing speed in VL\ulcornerSI implementation. In the application fields such as moving pictures experts group (MPEG) and joint photographic experts group (JPEG), 2-D DCT processor must be implemented precisely enough to meet the accuracy specifications of the ITU-T H.261. Almost all of 2-D DCT processors have been implemented using many multiplications and accumulations of matrices and vectors. The number of multiplications and accumulations seriously influence on comlexity and speed of 20D DCT processor. In 2-D DCT with fixed-point calculations, the computation bit width must be sufficiently large for the above accuracy specifications. It makes the reduction of hardware complexity hard. This paper proposes the accuracy compensator which compensates the accuracy of the finite word length calculation. 2-D DCT processor with the proposed accuracy compensator shows fairly reduced hardware complexity and improved processing speed.

• 대한전자공학회논문지
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• 제24권6호
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• pp.1040-1048
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• 1987

We propose a hardware architecture called Multiring which is applicable for various geometrical operations on rectilinear objects such as design rule checking in VLSI layout and many image processing operations including noise suppression and coutour extraction. It has both a fast execution speed and extremely high flexibility. The whole architecture is mainly divided into four parts` I/O between host and Multiring, ring memory, linear processor array and instruction decoder. Data transmission between host and Multiring is bit serial thereby reducing the bandwidth requirement for teh channel and the number of external pins, while each row data in the bit map stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 16 basic instructions such as Boolean (AND, OR, NOT, and Copy), geometrical(Expand and Shrink), and I/O operations each ring cycle, which gives Multiring maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of Multiring was confirmed by successfully running a software simulator having one-to-one structural correspondence to the Multiring hardware.

• Transactions on Electrical and Electronic Materials
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• 제18권6호
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• pp.320-322
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• 2017

In this paper, a high-performance, low-area gradient-magnitude calculator architecture is proposed, based on approximate image processing. To reduce the computational complexity of the gradient-magnitude calculation, vector properties, the symmetry axis, and common terms were applied in a hardware-resource-shared architec-ture. The proposed gradient-magnitude calculator was implemented using an Altera Cyclone IV FPGA (EP4CE115F29) and the Quartus II v.16 device software. It satisfied the output-data quality while reducing the logic elements by 23% and the embedded multipliers by 76%, compared with previous work.

• 전기학회논문지
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• 제57권2호
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• pp.320-326
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• 2008

In this paper, we propose a new algorithm emulating the DNA characteristics for noise-tolerant pattern matching problem on digital system. The digital pattern matching becomes core technology in various fields, such as, robot vision, remote sensing, character recognition, and medical diagnosis in particular. As the properties of natural DNA strands allow hybridization with a certain portion of incompatible base pairs, DNA-inspired data structure and computation technique can be adopted to bio-signal pattern classification problems which often contain imprecise data patterns. The key feature of noise-tolerance of DNA computing comes from control of reaction temperature. Our hardware system mimics such property to diagnose cardiovascular disease and results superior classification performance over existing supervised learning pattern matching algorithms. The hardware design employing parallel architecture is also very efficient in time and area.