• 제목/요약/키워드: generated voltage

검색결과 1,370건 처리시간 0.027초

Characteristics of the Voltages between the Communication Lines and Ground Induced by the Adjacent Artificial High-Voltage or Current ELF Source

  • Lee, Sang-Mu;Choi, Mun-Hwan;Cho, Pyung-Dong;Eun, Chang-Soo;Gimm, Yoon-Myoung
    • Journal of electromagnetic engineering and science
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    • 제9권4호
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    • pp.175-181
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    • 2009
  • The measurements were performed to verify experimentally that the voltage arising on a telecommunication line by a power line is due to the induction phenomena because there has been an opinion that the arising voltage on a telecommunication line is not by induction, but by other causality. The voltage appeared on the telecommunication line by way of an electric field or magnetic field generated by the source apparatus that had been artificially made to provide intentional constant high-voltage or current in ELF, that is, 60 Hz as an emulated commercial power.

UP/DOWN 변환이 동시에 지원되는 다중 전압 단일 출력 DC/DC 변환기 (A Multiple-Voltage Single-Output DC/DC Up/Down Converter)

  • 조상익;김정열;임신일;민병기
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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    • pp.207-210
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    • 2002
  • This paper describes a design of multiple-mode single-output DC/DC converter which can be used in both up and down conversion. Proposed up/down converter does not produce a negative voltage which is generated in conventional buck-boost type converter. Three types of operation mode(up/down/bypass) are controlled by the input voltage sense and command signals of target output voltage. PFM(pulse frequency modulation) control is adopted and modified for fast tracking and for precise output voltage level with an aid of output voltage sense. Designed DC/DC converter has the performance of less than 5 % ripple and higher than 80 % efficiency. Chip area is 3.50 mm ${\times}$ 2.05 mm with standard 0.35 $\mu\textrm{m}$ CMOS technology.

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향상된 고성능 VCDL(Voltage Controled Delay Line) (A Improved High Performance VCDL(Voltage Controled Delay Line))

  • 이지현;최영식;류지구
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2003년도 추계종합학술대회
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    • pp.394-397
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    • 2003
  • 최근의 system 내에서 동작속도가 급속히 증가함에 따라 단일 chip 내에서도 각부분의 clock 동기의 필요성이 요구되고 있다. 이러한 요구를 만족시키기 위해 PLL (Phase Locked Loop) 흑은 DLL (Delay Locked Loop)과 같은 clock를 동기 시켜 주는 회로가 사용되고 있다. PLL 내에서 주파수를 발생시키는 VCO (Voltage Controled Oscillator)는 jitter의 축적과 higher order system으로 인한 unstable한 특성과 설계하기 어렵다는 단점이 있다. 반면에 DLL에서 사용되는 VCDL (Voltage Controled Delay Line)은 first order system으로 동작이 stable하고 설계하기 쉬우며, no jitter의 장점을 가지고 있다. 본 연구에서는 기존의 VCDL의 단점을 개선하여 보다 안정적인 동작을 하는 VCDL을 제안하고자 한다.

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보상전압 첨가를 통한 B4 인버터 성능향상 (Performance Improvement of B4 Inverters by Adding Compensation Voltage)

  • 이동명
    • 전력전자학회논문지
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    • 제18권1호
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    • pp.110-116
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    • 2013
  • This paper proposes a current ripple reduction method to improve the control performance of B4 type inverter that is studied for cost-effective drive systems. B4 inverters employ only four switches and they have a center-tapped connection between the split dc-link capacitors and one phase of a three-phase motor or load. In the B4 topology, unbalanced three-phase voltages will be generated due to the dc-link voltage ripple. To solve this problem, this paper presents a voltage distortion compensation method that adjusts the voltage reference with the consideration of dc-link voltage ripple. The validity of the proposed method is verified by simulation and excremental results with an induction machine.

Design of a 6-bit 500MS/s CMOS A/D Converter with Comparator-based Input Voltage Range Detection Circuit

  • Dae, Si;Yoon, Kwang Sub
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권6호
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    • pp.706-711
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    • 2014
  • A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

발전영역을 갖은 자동형 brushless 충전발전기에 관한 연구 (The study of self excited type brushless charging generator, it has generated region)

  • 오병인
    • 전기의세계
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    • 제18권4호
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    • pp.7-15
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    • 1969
  • In this method the condenser excite winding has the phase angle of 90 electrical degree, with the load winding in stator. The condenser excite wing is connected with the condenser while the load winding is with the full rectifer. Direct and quardrature axis components of rotating field winding are composed, of balanced two phase winding, and each one of them is connected with half wave rectifiers. Initically, small amount of lead current can be induced at the condenser excite winding by residual magnetism of rotor. The induced lead current forces the rotating field winding to be excited by synchronous alternating magnetic field. The speed electromotive force, there for, induced in rotating field winding shall electro magnetize the rotating field pole by rotating half wave rectifiers. In the case of the charging generator directly coupled with engines at the operation of wide range speed, the generated region, such as vehicles, aircraft, ships etc, is occured. In conclusion, we can take the advantage of, omitting of voltage regurator and current limiter for charging load and reducing the consumption of fuel using the generated region which can be devided in to Impossible generated region, Generated region, and suspension generated region.

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Comparison of Multilevel Inverters Employing DC Voltage Sources Scaled in the Power of Three

  • Hyun, Seok-Hwan;Kwon, Cheol-Soon;Kim, Kwang-Soo;Kang, Feel-Soon
    • Journal of international Conference on Electrical Machines and Systems
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    • 제1권4호
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    • pp.457-463
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    • 2012
  • Cascaded H-bridge multilevel inverters shows a useful circuit configuration to increase the number of output voltage levels to obtain high quality output voltage. By applying the concept of the power of three to dc voltage sources, it can increase the number of output voltage levels effectively. To realize this concept, two approaches may be considered. One is to use independent dc voltage sources pre-scaled in the power of three, and the other is to use instantaneous dc voltage sources generated from a cascaded transformer, which has the secondary turn-ratios scaled in the power of three in sequence. A common feature in both approaches is to use the concept of the power of three for dc voltage sources, and a point of difference is whether it adopts a low frequency transformer or not, and where the transformer is located. According to the difference, application areas are limited and show different characteristics on THD of output voltages. We compare and analyze both approaches for their circuit configurations, voltage level generating method, THD characteristics of output voltage, efficiency, application areas, limitations, and other characteristics by experiments using 500 [W] prototypes when they generate a 27-level output voltage.

배압회로를 이용한 고승압 컨버터 (High Boost Converter Using Voltage Multiplier)

  • 백주원;김종현;류명효;유동욱;김종수
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제55권8호
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    • pp.416-422
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    • 2006
  • With the increasing demand for renewable energy, distributed power included in fuel cells have been studied and developed as a future energy source. For this system, a power conversion circuit is necessary to interface the generated power to the utility. In many cases, a high step-up dc/dc converter is needed to boost low input voltage to high voltage output. Conventional methods using cascade dc/dc converters cause extra complexity and higher cost. The conventional topologies to get high output voltage use flyback dc/dc converters. They have the leakage components that cause stress and loss of energy that results in low efficiency. This paper presents a high boost converter with a voltage multiplier and a coupled inductor. The secondary voltage of the coupled inductor is rectified using a voltage multiplier and series-connected with the boost voltage of primary voltage of the coupled inductor. Therefore, high boost voltage is obtained with low duty cycle. Theoretical analysis and experimental results verify the proposed solutions using a 300W prototype.

상전압 및 선간전압에 대한 불평형율 (Voltage Unbalance Factor for Phase and Line Voltage)

  • 김종겸;박영진;이동주;이종한;이은웅
    • 한국조명전기설비학회:학술대회논문집
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    • 한국조명전기설비학회 2005년도 춘계학술대회논문집
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    • pp.74-77
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    • 2005
  • Most of the loads in industrial power distribution systems are balanced and connected to three power systems. However, voltage unbalance is generated at the user's 3-phase 4-wire distribution systems with single & three phase. Voltage unbalance is mainly affected by load system rather than power system. Unbalanced voltage will draws a highly unbalanced current and results in the temperature rise and the low output characteristics at the machine. It is necessary to analyse correct voltage unbalance factor for reduction of side effects in the industrial sites. Voltage unbalance is usually defined by the maximum percent deviation of voltages from their average value, by the method of symmetrical components or by the expression in a more user-friendly form which requires only the three line voltage readings. If the neutral point is moved at the 3-phase 4-wire system by the unbalanced load, by the conventional analytical method, line and phase voltage unbalance leads to different results due to zero-sequence component. This paper presents a new analytical method for phase and line voltage unbalance factor in 4-wire systems. Two methods indicate exact results.

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A Hybrid Modular Multilevel Converter Topology with an Improved Nearest Level Modulation Method

  • Wang, Jun;Han, Xu;Ma, Hao;Bai, Zhihong
    • Journal of Power Electronics
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    • 제17권1호
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    • pp.96-105
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    • 2017
  • In this paper, a hybrid modular multilevel converter (MMC) topology with an improved nearest level modulation method is proposed for medium-voltage high-power applications. The arm of the proposed topology contains N series connected half-bridge submodules (HBSMs), one full-bridge submodule (FBSM) and an inductor. By exploiting the FBSM, half-level voltages are obtained in the arm voltages. Therefore, an output voltage with a 2N+1 level number can be generated. Moreover, the total level number of the inserted submodules (SMs) is a constant. Thus, there is no pulse voltage across the arm inductors, and the SM capacitor voltage is rated. With the proposed voltage balancing method, the capacitor voltage of the HBSM is twice the voltage of the FBSM, and each IGBT of the FBSM has a relatively low switching frequency and an equalized conduction loss. The capacitor voltage balancing methods of the two kinds of SMs are implemented independently. As a result, the switching frequency of the HBSM is not increased compared to the conventional MMC. In addition, according to a theoretical calculation of the total harmonic distortion of the electromotive force (EMF), the voltage quality with the presented method can be significantly enhanced when the SM number is relatively small. Simulation and experimental results obtained with a MMC-based inverter verify the validity of the developed method.