• 제목/요약/키워드: gating design

검색결과 79건 처리시간 0.027초

Computer Simulation에 의한 Semi-Solid 단조금형의 설계 및 실험적 검정 (Die Design of Semi-Solid Forging by Computer Simulation and their Experimental Investigation)

  • 서판기;이동훈;강충길
    • 한국소성가공학회:학술대회논문집
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    • 한국소성가공학회 2000년도 추계학술대회 논문집
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    • pp.185-190
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    • 2000
  • Die design by computer simulation has some advantages compared with the conventional method which has performed by designer's experiences and trials and errors. The die filling and solidification process of thixoforming process were simulated by MAGMAsoft/thixo module. First of all, thixoforming die design was applied to previously geometry shape. The value of pressure distribution shows high and uniform as the gate diameter is 18mm. Designed gating system considering the deformation of die and product was suggested by the filling simulation. Gate velocity(7.25m/s) of designed gating system shows that propriety to semi-solid metal working process and CAE results were in good agreement with experimental results.

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주형의 전산기 원용 설계 II -팅구계와 주형캐비티의 설계- (Computer Aided Design of a Mold Cavity with Proper Rigging System for Casting Processes(II))

  • 박종천;이건우
    • 대한기계학회논문집
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    • 제14권2호
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    • pp.376-381
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    • 1990
  • An interactive computer program to design a mold cavity with the proper rigging system has been developed. In addition to the pattern and the risers generated in part 1 of this work, the various components of the gating system are generated in complete three dimensional models by a rational approach. Then they are laid interactively by the user, and united together with the pattern and the risers to result in the three dimensional model of the mold assembly. Finally, the vents and the mold box are constructed following the user's interactive specification and then the mold cavity is completed in a three dimensional geometric model by subtraction the mold assembly and the vents from the mold box. The three dimensional model of a mold cavity is useful for many related applications such as the solidification simulation for mold evaluation and the NC tool path generation for mold production.

Design of 32 bit Parallel Processor Core for High Energy Efficiency using Instruction-Levels Dynamic Voltage Scaling Technique

  • Yang, Yil-Suk;Roh, Tae-Moon;Yeo, Soon-Il;Kwon, Woo-H.;Kim, Jong-Dae
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제9권1호
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    • pp.1-7
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    • 2009
  • This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

반용융 다이캐스팅 공정의 주조방안 설계 시스템 개발에 관한 연구 (A Study on Development Design System of Gating System for Semi-Solid Diecasting Process)

  • 문찬경;권택환;김영호;최재찬
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1997년도 추계학술대회 논문집
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    • pp.1028-1031
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    • 1997
  • The SS (Semi-solid) diecasters usually cany out the SS d~ecastmg experiments before producing new products. At the SS diecasting stages, the runner-gate part is always repeatedly corrected, which leads to a lengthened processing time and increased processing cost. The SS diecasting die design should consider component system factors. such as runner, gate, biscuit, overflow and airvent. A large amount of experience is essential in manual assessment and if the design is defective, much time and a great deal of efforts will be wasted in the modification of the d~e. Thus human negligence should be minimized. In this study, die design system for SS diecasting process has been developed to present algonthm of die design, especially runner-gate system. In addition, specific rules and equations for runner-gate system have been presented to avoid too many trials and errors with expensive equipment. It is possible for engineers to be efficient die design of SS diecasting and it will result in reduction of expense and time to be required. And we developed CAD system for SS diecasting die design by AutoLISP language under AutoCAD using proposed algorithm and the database. In addition, we developed the vector analysis program for filling pattern of SS metals.

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필터방식 얼굴검출 하드웨어의 저전력 설계 (Low Power Design of Filter Based Face Detection Hardware)

  • 김윤구;정용진
    • 대한전자공학회논문지SD
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    • 제45권6호
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    • pp.89-95
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    • 2008
  • 본 논문에서는 필터방식 얼굴검출 하드웨어를 저전력 설계하고 그에 따른 전력 소모량을 분석하였다. 얼굴검출 하드웨어는 입력되는 영상에서 얼굴의 위치를 검출하며 내부적으로 6개 모듈과 11개의 모듈 간 버퍼가 삽입되어 각 모듈이 순환 연산한다. 따라서 저전력 설계를 위해 SLEEP 모드와 ACTIVE 모드를 적용하였고, 해당 하드웨어에 모듈별 그리고 레지스터별 클럭게이팅(Clock Gating) 기술을 적용하였다. 추가적으로 모듈간 버퍼는 메모리 파티션을 통해 메모리에서 소비하는 전력양을 줄였으며 게이트 레벨에서도 저전력 설계 기술(Gate level power optimization)을 적용하였다. 이는 삼성 0.18um 공정의 STD130 라이브러리를 사용하여 Synopsis(사)의 Power-Compiler를 통해 구현되었으며 동사의 Prime-Power에 의해 소비 전력량을 측정하였다. 그 결과 저전력 설계 기술을 적용하기 전과 비교하여 ACTIVE 모드일 경우 약 68%의 전력 소모를 줄였다.

ODC 클럭 게이팅을 이용한 저전력 Interface 회로설계 (Design of Low- Power Interface using Clock Gating Based on ODC Computation)

  • 양현미;김희석
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2008년도 하계종합학술대회
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    • pp.597-598
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    • 2008
  • In this paper, a sample design of I/O port of micro-processor using ODC(Output Don't Care) computation that is one of methods for Clock Gating applicable at the register transfer level(RTL). The ODC computation Method is applied at the point that estimate the value considering Don't Care Conditions from output of datapath to registers using clock in logic system. This paper also shows the results of reduce consumption power due to controlling clock that was supplied at registers. In Experimental results, ODC computation Method reduce power reductions of around 37.5%

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반응고 주조공정에서 평면도 증대를 위한 게이트시스템의 강건설계 (Robust Design of the Gate System for Flatness Improvement in Semi-Solid Casting Processes)

  • 송인호;정성종
    • 한국공작기계학회논문집
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    • 제18권2호
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    • pp.130-136
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    • 2009
  • Semi-solid casting(SSC) of magnesium alloys is increasingly being used to produce high quality components. This process is similar to the injection molding of plastics and is called thixomolding. Using this process, higher strength, thinner wall sections and tighter tolerances without porosity are obtained. The high strength and low weight characteristics of magnesium alloys render the high-precision fabrication of thin-walled components with large surface areas. They are widely used for the IT, auto and consumer electronics industries. However, warpage of the thin-walled sections degrade quality of the parts produced in the SCC process. To produce thin-walled magnesium alloy parts, the geometry of gating system on the quality of the finished products should be clearly studied. In this paper, to minimize warpage of the thin-walled sections, Taguchi method is applied to the optimal design of the gate geometry in the thixomolding process. Width, height, length and angle of the gating system are selected for the robust design parameters. Effectiveness of the robust design is verified through the CAE software.

게이트 수에 따른 단조형 인서트와 주물재 사이의 경계부 특성 분석 (Effect of Gate Number on the Characteristics of Interface between Cast and Forged Insert)

  • 이성문;이혜경;이건엽;문성민;문영훈
    • 열처리공학회지
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    • 제22권2호
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    • pp.95-100
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    • 2009
  • In this study, the casting process using forged insert was investigated to characterize the manufacturing process by which good mechanical properties can be obtained when compared with existing casting products. Process analysis for the casting design was performed by using FVM (Finite Volume Method) software. In pouring process, three kinds of candidate gating systems are considered and analyzed respectively. The molten metal behavior in gating system is so important that it affects the solidification behavior of the cast. The results show that as the number of gates is increased, hardness of cast was increased and gaps of cast with forged insert were decreased.

${\alpha}{\beta}$ 필터 및 NNPDA 알고리즘을 이용한 차량용 레이더 표적 추적 시스템 설계 (An Automotive Radar Target Tracking System Design using ${\alpha}{\beta}$ Filter and NNPDA Algorithm)

  • 배준형;현유진;이종훈
    • 대한임베디드공학회논문지
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    • 제6권1호
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    • pp.16-24
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    • 2011
  • Automotive Radar Systems are currently under development for various applications to increase accuracy and reliability. The target tracking is most important in single or multiple target environments for accuracy. The tracking algorithm provides smoothed and predicted data for target position and velocity(Doppler). To this end, the fixed gain filter(${\alpha}{\beta}$ filter, ${\alpha}{\beta}{\gamma}$ filter) and dynamic filter(Kalman filter, Singer-Kalman filter, etc) are commonly used. Gating is used to decide whether an observation is assigned to an existing track or new track. Gating algorithms are normally based on computing a statistical error distance between an observation and prediction. The data association takes the observation-to-track pairings that satisfied gating and determines which observation-to-track assignment will actually be made. For data association, NNPDA(Nearest Neighbor Probabilistic Data Association) algorithm is proposed. In this paper, we designed a target tracking system developed for an Automotive Radar System. We show the experimental results of the 77GHz FMCW radar sensor on the roads. Four tracking algorithms(${\alpha}{\beta}$ filter, ${\alpha}{\beta}{\gamma}$ filter, 2nd order Kalman filter, Singer-Kalman filter) have been compared and analyzed to evaluate the performance in test scenario.

수치해석에 의한 고압다이캐스팅용 금형설계 및 주조공정해석 (Analysis of the High Pressure Die Casting Process by Computer Simulation)

  • 이창호;최재권;남태운
    • 한국주조공학회지
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    • 제20권6호
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    • pp.400-406
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    • 2000
  • Computer simulation for the predictions of casting defects is very important to produce high quality castings with less cost. Complicate shaped Al solenoid housing part was selected to be cold chamber die cast and a numerical simulation technique was applied for the optimization of the chill vent position and gating. A first design led to insufficient central flow. This flow left the last filled areas falling into the inner portion of the part. And last filled area did not fit the chill vent position. So these resulted in a high possibility of air entrapment in the casting and the design was not proper for the part. The design was improved by using a proper gating system, a more chill vent and proper overflow positions. New design provided a homogenous mold filling pattern and the last filled areas that being located at the overflow and chill vent. Casting plan which produce good quality solenoid housing part was established by using the computer simulation.

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