• 센서학회지
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• 제26권4호
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• pp.292-296
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• 2017

It has become ever harder to design reliable circuits with each nanometer technology node under normal operation conditions, a transistor device can be affected by various aging effects resulting in performance degradation and eventually design failure. The reliability (aging) effect has traditionally been the area of process engineers. However, in the future, even the smallest of variations can slow down a transistor's switching speed, and an aging device may not perform adequately at a very low voltage. Because of such dilemmas, the transistor aging is emerging as a circuit designer's problem. Therefore, in this paper, the impact of aging effects on the delay and power dissipation of digital circuits by using nanomneter MOSFET power gating structure has been analyzed.. Based on this analyzed aging models, a reliable digital circuits can be designed.

• 한국산업융합학회 논문집
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• 제24권5호
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• pp.597-608
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• 2021

The control head components used in small military vessels are designed to be domestically produced, prototypes, structural analysis, and casting methods are designed and cast. The control head assembly consists of a lever, an aluminum outside cover, Middle, front gear cover, back gear cover, and a zinc worm gear. In order to reverse the design of each component, 3D scanning device was used, 3D modeling was performed by CATIA, and prototype productions were carried out by 3D printer. In order to reduce the cost of components, gating system is used by gravity casting method. The SRG ratio of 1:0.9:0.6 was set by applying non-pressurized gating system to aluminum parts, 1:2.2:2.0 and pressurized gating system to zinc parts, and the shapes of sprue, runner and gate were designed. The results of porosity were also confirmed by casting analysis in order to determine whether the appropriate gating system can be designed. The results showed that all parts started solidification after filling completely. ANSYS was used for structural analysis, and the results confirmed that all five components had a safety factor of 15 more. All castings are free of defects in appearance, and CT results show only very small porosity. ZnDC1 zinc alloy worm gear has a tensile strength of 285 MPa and an elongation of 8%. The tensile strength of the four components of A356 aluminum alloy is about 137-162 MPa and the elongation is 4.8-6.5%.

• 한국산업융합학회 논문집
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• 제24권5호
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• pp.589-596
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• 2021

In this study, the optimum gating system was designed, and the two zinc alloy worm gears were manufactured in single process by applying a symmetrical gating system with 2 runners. The SRG ratio is set to 1 : 0.9 : 0.6, and the cross-sectional shapes such as sprue, runner and gate are designed. In order to determine whether the design of the gating system is appropriate, casting analysis was carried out. It takes 4.380 s to charge the casting 100%, 0.55 to 0.6 m/s at the gates and solidification begins after the casting is fully charged. The amount of air entrapment is 2% in the left gear and 6% in the right gear. Hot spots occurred in the center hole of the gear, and pores were found to occur around the upper part of the hole. Therefore, the design of the casting method is suitable for worm gears. CT analysis showed that all parts of worm gear were distributed with fine pores and some coarse pores were distributed around the central hole of worm gear. The yield strength and tensile strength were 220 MPa, 285 MPa, and the elongation rate was 8%. Vickers hardness is 82 HV.

• 전자통신동향분석
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• 제35권2호
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• pp.69-78
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• 2020

Small portable devices such as mobile phones and laptops currently display a trend of high power consumption owing to their characteristics of high speed and multifunctionality. Low-power SoC design is one of the important factors that must be considered to increase portable time at limited battery capacities. Popular low power SoC design techniques include clock gating, multi-threshold voltage, power gating, and multi-voltage design. With a decreasing semiconductor process technology size, leakage power can surpass dynamic power in total power consumption; therefore, appropriate low-power SoC design techniques must be combined to reduce power consumption to meet the power specifications. This study examines several low-power SoC design trends that reduce semiconductor SoC dynamic and static power using EDA tools. Low-power SoC design technology can be a competitive advantage, especially in the IoT and AI edge environments, where power usage is typically limited.

• 한국주조공학회지
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• 제37권3호
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• pp.71-77
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• 2017

Casting defects produced during the casting process seriously affect the mechanical properties of the resulting products, reduce the performance capabilities of the product, and also result in economic losses. Therefore, this paper mainly investigates the causes of defects and methods by which to reduce these defects stemming from molten metal flows in a runner system of the type widely used in the sand mold casting process. The flow characteristics of a molten alloy are difficult to observe during the actual casting process. For this reason, a water model was used to observe the flow in the casting process, and the flow in each case was recorded using high-speed cameras as part of the experimental process of this study. Several repetitive experiments were performed to improve the accuracy of the experimental results. The traditional casting system was modified according to the design rules proposed by Campbell, and the system was termed flow-adaptive gating system with a water model. Comparing the flow characteristics of traditional and adaptive gating systems with a water model shows that the bubbles in the water in the latter case are reduced more significantly than in the former case. A ceramic filter system was adapted to the flow-adaptive gating system to minimize the instability of the flow during filling, which occurs as the fluid velocity in the runner increases. In additional, the flow behavior with and without the filter system were compared. The water model system in this work was shown to be able to verify that the adaptation of the filter system brings improvements by stabilizing the flow and reducing the amount of bubbles in the runner system. Moreover, using the flow-adaptive runner system with the filter system leads to considerably stable flows in the runner system.

• 대한전자공학회논문지SD
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• 제42권10호
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• pp.1-8
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• 2005

본 논문에서는 강유전체 메모리의 셀 효율을 높이기 위해 PMOS-gating 셀을 이용한 설계기법을 기술하였다. PMOS-gating 셀은 PMOS access 트랜지스터와 강유전체 커패시터로 이루어지며 커패시터의 플레이트는 ground에 고정된다. 아울러 read/write 동작시 비트라인이 $V_{DD}$로 precharge 되고, negative 전압 워드라인 기법이 사용되며, negative 펄스 restore 동작을 이용한다. 이는 셀 플레이트 구동없이 단순히 워드라인과 비트라인만 구동하여 메모리 셀의 데이타를 저장하고 읽어낼 수 있는 설계 방식으로, 기존의 셀 플레이트를 구동하는 FRAM 대비 메모리 셀 효율을 극대화 할 수 있어, multi-megabit 이상의 집적도에서 경쟁력 있는 칩 면적 구현이 가능하다. $0.25-{\mu}m$ triple-well 공정을 적용한 2.5-V, 1-Mb FRAM 시제품 설계를 통해 제안한 설계기술을 검증하였고, 시뮬레이션 결과 48 ns의 access time, 11 mA의 동작전류 특성을 보였다. 레이아웃 결과 칩 면적은 $3.22\;mm^{2}$ 이며, 기존의 셀 플레이트 구동기를 사용하는 FRAM 대비 약 $20\;\%$의 셀 효율을 개선하였다.

• 한국정보통신학회논문지
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• 제12권3호
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• pp.555-562
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• 2008

본 논문에서는 RTL 수준에서의 클록 게이팅을 이용한 실제적인 저전력 설계 기술에 대해서 제안하고자 한다. 상위 수준의 회로 설계자에 의해 시스템의 동작을 분석하여 클록 게이팅을 위한 제어기를 이용하는 것이 가장 효율적인 전력 감소를 가져 온다. 또한 직접적으로 클록 게이팅을 수행하는 것보다는 합성툴이 자연스럽게 게이팅된 클록을 맵핑할 수 있도록 RTL 수준에서 유도하는 것이 바람직하다. RTL 코딩 단계에서부터 저전력이 고려되었다면 처음 코딩단계에서부터 클록을 게이팅 시키고, 만일 고려되지 않았다면 동작을 분석한 후에 대기 동작인 부분에서 클록을 게이팅 한다. 그리고 회로의 동작을 분석한 후에 클록의 게 이팅을 제어하기 위한 제어기를 설계하고 합성 툴에 의해 저전력 회로에 해당하는 netlist를 얻는다. 결과로부터 상위수준의 클록 게이팅에 의해 레지스터의 전력이 922 mW에서 543 mW로 42% 감소한 것을 확인할 수 있다. Power Theater 자체의 synthesizer를 이용하여 netlist로 합성한 후에 전력을 측정했을 경우에는 레지스터의 전력이 322 mW에서 208 mW로 36.5% 감소한 것을 확인할 수 있다.

• 전자공학회논문지
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• 제52권10호
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• pp.56-63
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• 2015

SoC (System-on-Chip) 설계초기 상위수준에서 성능뿐만 아니라 전력 분석이 중요하다. 본 논문에서는 상위수준에서 전력 분석 정확도가 높은 클럭 게이팅 구동 신호 기반 전력 모델을 제안한다. 클럭 게이팅 구동 신호의 조합으로 전력 상태를 정의하며, 클럭 게이팅 구동 신호를 자동으로 추출하여 전력 모델을 자동으로 생성할 수 있다. 실험 결과 평균 96% 이상의 정확도를 보였으며, 상위수준에서의 전력 분석 속도는 게이트 수준 대비 평균 280배 빠른 속도향상을 보였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.904-905
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• 2008

In this paper, a novel 60kV, 300A, 3kHz pulsed power supply based on IGBT stacks is proposed. Proposed scheme consists of series connected 9 power stages to generate maximum 60kV output pulse and 15kW series resonant power inverter to charge DC capacitor voltage. Each power stages are configured as 8 series connected power cells and each power cell generates up to 830VDC, 300A pulses. Finally pulse output voltage is applied using total 72 series connected IGBTs. The synchronization of gating signal is important of series operation of IGBTs. For gating signal synchronization, full bridge inverter and pulse transformer generates on-off signals of IGBT gating and specially designed gate power circuit was used.

• 정보처리학회논문지A
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• 제12A권1호
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• pp.1-6
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• 2005

본 논문에서는 trace-back systolic array Viterbi algorithm의 저전력 생존 메모리 구현에 관한 새로운 알고리즘을 소개한다. 이 알고리즘의 핵심 아이디어는 trace back 연산의 수를 줄이기 위하여 이미 생성된 trace-back routes를 재사용하는 것이다. 그리고 trace-back unit의 불필요한 switching activity가 발생하는 영역을 gate-clock을 사용하여 전력소모를 줄이는 것이다. Synopsys Power Estimation 툴인 Design Power를 이용하여 전력소모를 측정하였고, 그 결과 [1]의 논문에서 소개된 trace-back unit 비하여 평균 $40{\%}$ 전력감소가 있었고, $23{\%}$의 면적증가를 보였다.