DOI QR코드

DOI QR Code

Analysis of Aging Phenomena in Nanomneter MOSFET Power Gating Structure

나노미터 MOSFET 파워 게이팅 구조의 노화 현상 분석

  • Lee, Jinkyung (Department of Electronic Engineering, Daegu University) ;
  • Kim, Kyung Ki (Department of Electronic Engineering, Daegu University)
  • Received : 2017.07.16
  • Accepted : 2017.07.27
  • Published : 2017.07.31

Abstract

It has become ever harder to design reliable circuits with each nanometer technology node under normal operation conditions, a transistor device can be affected by various aging effects resulting in performance degradation and eventually design failure. The reliability (aging) effect has traditionally been the area of process engineers. However, in the future, even the smallest of variations can slow down a transistor's switching speed, and an aging device may not perform adequately at a very low voltage. Because of such dilemmas, the transistor aging is emerging as a circuit designer's problem. Therefore, in this paper, the impact of aging effects on the delay and power dissipation of digital circuits by using nanomneter MOSFET power gating structure has been analyzed.. Based on this analyzed aging models, a reliable digital circuits can be designed.

Keywords

References

  1. B. Paul, K. Kang, H. Kufluoglu, M. Ashraful Ala.m, K. Roy, "Temporal Performance Degradation Under NBTI: Estimation And Design For Improved Reliability Of Nanoscale Circuits", Vol. 1, pp. 1-6, March 2006.
  2. Intel, "3-D, 22nm: New Technology Delivers An Unprecedented Combination of Performance and Power Efficiency", http://www.intel.com/content/www/us/en/ siliconinnovations/ intel-22nm-technology.html, 2012.
  3. Mostafa, H.; Anis, M.; Elmasry, M., "NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias," Semiconductor Manufacturing, IEEE Transactions on, Vol.25, No.3, pp.460,467, 2012.
  4. S. V. Kumar, C. H. Kim, S. S. Sapatnekar, "Adaptive techniques for overcoming performance degradation due to aging in CMOS circuits," in Proc. IEEE ASP-DAC, Jan. 2009, pp. 284-289.
  5. F. Arnaud, J. Liu, Y. M. Lee, et. al. "32nm general purpose bulk CMOS technology for high performance applications at low voltage," IEEE IEDM'08, pp. 1-4, Dec. 2008.
  6. S. Sahhaf, R. Degraeve, P. J. Roussel, B. Kaczer, T. Kauerauf, G. Groeseneken, "A new TDDB reliability prediction methodology accounting for multiple SBD and wear out," IEEE Trans. On Electron Devices, Vol. 56, Issue 7, pp. 1424-1432, July 2009. https://doi.org/10.1109/TED.2009.2021810
  7. S. Sahhaf, R. Degraeve, P. J. Roussel, B. Kaczer, T. Kauerauf, G. Groeseneken, "A new TDDB reliability prediction methodology accounting for multiple SBD and wear out," IEEE Trans. On Electron Devices, Vol. 56, Issue 7, pp. 1424-1432, July 2009. https://doi.org/10.1109/TED.2009.2021810
  8. M. Rajesh, G. Vinod, D. Das, P. Bhatnagar, C. Pithawa, A. Thaduri, And A. Verma, "A Study Of Failure Mechanisms In CMOS And Bjt Ics And Their Effect On Device Reliability", In 2nd International Conference on Reliability, Safety and Hazard, December 2010.
  9. K. K. Kim, H. Nan, and K. Choi, "Power gating for ultralow voltage nanometer ICs," in Proc. IEEE Int Circuits and Systems (ISCAS) Symp, pp. 1472-1475, 2010.