• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.4
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• pp.208-212
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• 2004

In this paper, the characteristics of co-sputtered Ru-Zr metal alloy as gate electrode of MOS capacitors have been investigated. The atomic compositions of alloy were varied by using the combinations of relative sputtering power of Ru and .Zr. C-V and I-Vcharacteristics of MOS capacitors were measured to find the effective oxide thickness and work function. The alloy made of about 50% of Ru and 50% of Zr exhibited an adequate work function for nMOS. C-V and I-V measurements after 600 and $700^{\circ}C$ rapid thermal annealing were performed to prove the thermal and chemical stability of the Ru-Zr alloy film. Negligible changes in the accumulated capacitance and work function before and after annealing were observed. Sheet resistance of Ru-Zr alloy was lower than that of poly-silicon. It can be concluded that the Ru-Zr alloy can be a possible substitute for the poly-silicon used as a gate of nMOS.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.261-266
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• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.37-40
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• 1999

For the first time, charge trapping nonvolatile semiconductor memories with the deoxidized oxynitride gate dielectric is proposed and demonstrated. Gate dielectric wit thickness of less than 1 nm have been grown by postnitridation of pregrown thermal silicon oxides in NO ambient and then reoxidation. The nitrogen distribution and chemical state due to NO anneal/reoxidation were investigated by M-SIMS, TOF-SIMS, AES depth profiles. When the NO anneal oxynitride film was reoxidized on the nitride film, the nitrogen at initial oxide interface not only moved toward initial oxide interface, but also diffused through the newly formed tunnel oxide by exchange for oxygen. The results of reoxidized oxynitride(ONO) film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/N-rich SiON interface/Si-rich SiON(nitrogen diffused tunnel oxide)/Si substrate. In addition, the SiON and the S1$_2$NO Phase is distributed mainly near the tunnel oxide, and SiN phase is distributed mainly at tunnel oxide/Si substrate interface.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.3
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• pp.34-40
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• 1999

Recently, the gate oxide damage induced by the plasma processes has been one of the most significant reliability issues as the gate oxide thickness falls below 10 nm. The plasma-induced damage was studied with the metal antenna test structures. In addition to the electron trapping, the hole trapping in a 10 nm thick gate oxide due to the plasma-induced charging was observed in the NMOS's with a metal antenna. The hole trapping caused the transconductance (gm) to be reduced like the case of the electron trapping, but to the extent much less than the electron trapping. It would be because the electrical stress that the plasma-induced charging forced to the gate oxide for the devices with the hole trapping was much smaller than for those with the electron trapping. This hypothesis was strongly supported by the measured characteristics of the Fowler-Nordheim current in the gate oxide.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.2
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• pp.1-6
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• 1983

The reduction of threshold voltage and punchthrough voltage of short channel MOS transistors has been measured experimentally with silicon gate NMOS transistors. The effects of the gate oxide thickness and substrate doping concentration on the threshold voltage and punch-through voltage have also been measured with sample devices with boron implantation and gate oxide thickness of 50 nm and 70 nm. Hot electron emission has been measured by floating gate method for the samples with 3 ${\mu}{\textrm}{m}$ channel length. It has been concluded from this measurement that hot electron emission is not significant for the channel length of 3${\mu}{\textrm}{m}$.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.463-463
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• 2012

ITRS (international technology roadmap for semiconductors)에 따르면 MOS(metal-oxide-semiconductor)의 CD (critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/$SiO_2$를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두된다고 보고하고 있다. 일반적으로 high-k dielectric를 식각시 anisotropic 한 식각 형상을 형성시키기 위해서 plasma를 이용한 RIE (reactive ion etching)를 사용하고 있지만 PIDs (plasma induced damages)의 하나인 PIED (plasma induced edge damage)의 발생이 문제가 되고 있다. PIED의 원인으로 plasma의 direct interaction을 발생시켜 gate oxide의 edge에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 high-k dielectric의 식각공정에 HDP (high density plasma)의 ICP (inductively coupled plasma) source를 이용한 원자층 식각 장비를 사용하여 PIED를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. One-monolayer 식각을 위한 1 cycle의 원자층 식각은 총 4 steps으로 구성 되어 있다. 첫 번째 step은 Langmuir isotherm에 의하여 표면에 highly reactant atoms이나 molecules을 chemically adsorption을 시킨다. 두 번째 step은 purge 시킨다. 세 번째 step은 ion source를 이용하여 발생시킨 Ar low energetic beam으로 표면에 chemically adsorbed compounds를 desorption 시킨다. 네 번째 step은 purge 시킨다. 결과적으로 self limited 한 식각이 이루어짐을 볼 수 있었다. 실제 공정을 MOS의 high-k dielectric에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU (North Carolina State University) CVC model로 구한 EOT (equivalent oxide thickness)는 변화가 없으면서 mos parameter인 Ion/Ioff ratio의 증가를 볼 수 있었다. 그 원인으로 XPS (X-ray photoelectron spectroscopy)로 gate oxide의 atomic percentage의 분석 결과 식각 중 발생하는 gate oxide의 edge에 trap의 감소로 기인함을 확인할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.228-239
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• 2004

In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.6
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• pp.1399-1404
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• 2015

This paper analyzed the phenomenon of drain induced barrier lowering(DIBL) for the ratio of channel length vs. thickness of asymmetric double gate(DG) MOSFET. DIBL, the important secondary effect, is occurred for short channel MOSFET in which drain voltage influences on potential barrier height of source, and significantly affects on transistor characteristics such as threshold voltage movement. The series potential distribution is derived from Poisson's equation to analyze DIBL, and threshold voltage is defined by top gate voltage of asymmetric DGMOSFET in case the off current is 10^-7 A/m. Since asymmetric DGMOSFET has the advantage that channel length and channel thickness can significantly minimize, and short channel effects reduce, DIBL is investigated for the ratio of channel length vs. thickness in this study. As a results, DIBL is greatly influenced by the ratio of channel length vs. thickness. We also know DIBL is greatly changed for bottom gate voltage, top/bottom gate oxide thickness and channel doping concentration.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.748-751
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• 2014

This paper has analyzed threshold voltage movement for channel doping concentration of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is generally fabricated with low doping channel and fully depleted under operation. Since impurity scattering is lessened, asymmetric DGMOSFET has the adventage that high speed operation is possible. The threshold voltage movement, one of short channel effects necessarily occurred in fine devices, is investigated for the change of channel doping concentration in asymmetric DGMOSFET. The analytical potential distribution of series form is derived from Possion's equation to obtain threshold voltage. The movement of threshold voltage is investigated for channel doping concentration with parameters of channel length, channel thickness, oxide thickness, and doping profiles. As a result, threshold voltage increases with increase of doping concentration, and that decreases with decrease of channel length. Threshold voltage increases with decrease of channel thickness and bottom gate voltage. Lastly threshold voltage increases with decrease of oxide thickness.

• Korean Journal of Materials Research
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• v.13 no.11
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• pp.711-716
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• 2003

Gate length, height, and silicide thickness have all been shrinking linearly as device density has progressively increased over the years. We investigated the effect of the cobalt diffusion during the silicide formation process on the 60$\AA$-thick gate oxide lying underneath the Ti/Co and Co/Ti bilayers. We prepared four different cobalt silicides, which have similar sheet resistance, made from the film structure of Co/Ti(interlayer), and Ti(capping layer)/Co, and peformed the current-voltage, time-to-break down, and capacitance-voltage measurements. Our result revealed that the cobalt silicide process without the Ti capping layer allowed cobalt atoms to diffuse into the upper interface of gate oxides. We propose that 100$\AA$-thick titanium interlayer may lessen the diffusion of cobalt to gate oxides in 1500-$\AA$ height polysilicon gates.