• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.6
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• pp.1123-1127
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• 2009

This paper expands the scope of application of the thin film transistor (TFT) in which it is used as the switching element by making the amorphous silicon TFT with the non-volatile memory device,. It is the thing about the amorphous silicon non-volatile memory device which is suitable to an enlargement and in which this uses the additionally cheap substrate according to the amorphous silicon use. As to, the amorphous silicon TFT non-volatile memory device is comprised of the glass substrates and the gate, which evaporates on the glass substrates and in which it patterns the first insulation layer, in which it charges the gate the floating gate which evaporates on the first insulation layer and in which it patterns and the second insulation layer in which it charges the floating gate, and the active layer, in which it evaporates the amorphous silicon on the second insulation layer the source / drain layer which evaporates the n+ amorphous silicon on the active layer and in which it patterns and the source / drain layer electrode in which it evaporates on the source / drain layer.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.359-363
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• 2005

The organic insulation devices with MIM (metal-insulator-metal) structures as PVP gate insulation films were prepared for the application of organic thin film transistors (OTFT). The co-polymer organic insulation films were synthesized by using PVP(poly-4-vinylphenol) as solute and PGMEA (propylene glycol monomethyl ether acetate) as solvent. The cross-linked PVP insulation films were also prepared by addition of poly (melamine-co-formaldehyde) as thermal hardener. The leakage current of the cross-linked PVP films was found to be about 300 pA with low current noise. and showed better property in electrical properties as compared with the co-polymer PVP insulation films. In addition, cross-linked PVP insulation films showed better surface morphology (roughness), showing about 0.11${\~}$0.18 nF in capacitance for all PVP film samples.

• ETRI Journal
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• v.35 no.3
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• pp.425-430
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• 2013

In this paper, we propose a triple-gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage ($BV_{DS}$) and on-state current ($I_{D,MAX}$), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer ($SiO_2$) of a conventional RSO power MOSFET is changed to a multilayered insulator ($SiO_2/SiN_x/TEOS$). The inserted $SiN_x$ layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and the poly-Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as $BV_{DS}$ and $I_{D,MAX}$, simulation studies are performed on the function of the gate configurations and their bias conditions. $BV_{DS}$ and $I_{D,MAX}$ are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15-V gate voltage. This $I_{D,MAX}$ variation indicates the specific on-resistance modulation.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.12
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• pp.755-760
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• 1999

Various fluoride films were investigated for a gate insulator of thin film transistor application. Conventional oxide containing materials like $SiO_2\;Ta_2O_5\; and \; Al_2O_3$ exhibited high interface states which lead to an increased threshold voltage and poor stability of TFT. In this paper, we investigated gate insulators using a binary matrix system of fluoride such as $CaF_2,\; SrF_2\; MgF_2,\; and\; BaF_2$. These materials exhibited an improvement in lattice mismatch, interface state and electrical stability. MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 5%, breakdown electric field higher than 1.2MV/cm and leakage current density of $10^{-7}A/cm^2$. MIS diode having $Ca_2$ film as an insulation layer exhibited the interface states as low as $1.58\times10^{11}cm^{-2}eV^{-1}$. This paper probes a possibility of new gate insulator materials for TFT applications.

• Journal of the Korean Vacuum Society
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• v.22 no.3
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• pp.131-137
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• 2013

The thin insulator films for organic memory device were made by the plasma polymerization method using the styrene monomer which was not the wet process but the dry process. For the formation of stable plasma, we make an effort for controlling the monomer with bubbler and circulator system. The thickness of plasma polymerized styrene insulator layer was 430 nm, the thickness of the Au memory layer was 7 nm thickness of plasma polymerized styrene tunneling layer was 30, 60 nm, the thickness of pentacene active layer was 40 nm, the thickness of source and drain electrodes were 50 nm. The I-V characteristics of fabricated memory device got the hysteresis voltage of 45 V at 40/-40 V double sweep measuring conditions. If it compared with the results of previous paper which was the organic memory with the plasma polymerized MMA insulation thin film, this result was greater than 18 V, the improving ratio is 60%. From the paper, styrene indicated a good charge trapping characteristics better than MMA. In the future, we expect to make the organic memory device with plasma polymerized styrene as the memory thin film.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.87-91
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• 2024

SiO₂, renowned for its excellent insulating properties, has been used in the semiconductor industry as a valuable dielectric material. High-quality SiO₂ films find applications in gate spacers and interlayer insulation gap-fill oxides, among other uses. One of the prevalent methods for depositing these SiO₂ films is plasma enhanced chemical vapor deposition (PECVD) favored for its relatively low processing costs and ability to operate at low temperatures. However, compared to the increasingly utilized atomic layer deposition (ALD) method, PECVD exhibits inferior film characteristics such as uniformity. This study aims to produce SiO₂ films with uniformity as close as possible to those achieved by ALD through the adjustment of PECVD process parameters. we conducted a total of nine PECVD processes, varying the process time and gas flow rates, which were identified as the most influential factors on the PECVD process. Furthermore, ellipsometry analysis was employed to examine the uniformity variations of each process. The experimental results enabled us to elucidate the relationship between uniformity and deposition rate, as well as the impact of gas flow rate and deposition time on the process outcomes. Additionally, thickness measurements obtained through ellipsometer facilitate the identification of optimal process parameters for PECVD.

• Nuclear Engineering and Technology
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• v.56 no.9
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• pp.3740-3749
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• 2024

To reduce the losses caused by aging failure of insulation gate bipolar transistor (IGBT), which is the core components of nuclear power plant rod position indicating and rod control (RPC) system. It is necessary to conduct studies on its life prediction. The selection of IGBT failure characteristic parameters in existing research relies heavily on failure principles and expert experience. Moreover, the analysis and learning of time-domain degradation data have not been fully conducted, resulting in low prediction efficiency as the monotonicity, time correlation, and poor anti-interference ability of extracted degradation features. This paper utilizes the advantages of the stacked denoising autoencoder(SDAE) network in adaptive feature extraction and denoising capabilities to perform adaptive feature extraction on IGBT time-domain degradation data; establishes a long-short-term memory (LSTM) prediction model, and optimizes the learning rate, number of nodes in the hidden layer, and number of hidden layers using the Gray Wolf Optimization (GWO) algorithm; conducts verification experiments on the IGBT accelerated aging dataset provided by NASA PCoE Research Center, and selects performance evaluation indicators to compare and analyze the prediction results of the SDAE-LSTM model, PSOLSTM model, and BP model. The results show that the SDAE-LSTM model can achieve more accurate and stable IGBT life prediction.