The Study on the Uniformity, Deposition Rate of PECVD SiO2 Deposition

  • Eun Hyeong Kim (Department of Electronics Engineering, Myongji University) ;
  • Yoon Hee Choi (Department of Electronics Engineering, Myongji University) ;
  • Hyeon Ji Jeon (Department of Electronics Engineering, Myongji University) ;
  • Woo Hyeok Jang (Department of Electronics Engineering, Myongji University) ;
  • Garam Kim (Department of Electronics Engineering, Myongji University)
  • Received : 2024.06.05
  • Accepted : 2024.06.21
  • Published : 2024.06.30

Abstract

SiO2, renowned for its excellent insulating properties, has been used in the semiconductor industry as a valuable dielectric material. High-quality SiO2 films find applications in gate spacers and interlayer insulation gap-fill oxides, among other uses. One of the prevalent methods for depositing these SiO2 films is plasma enhanced chemical vapor deposition (PECVD) favored for its relatively low processing costs and ability to operate at low temperatures. However, compared to the increasingly utilized atomic layer deposition (ALD) method, PECVD exhibits inferior film characteristics such as uniformity. This study aims to produce SiO2 films with uniformity as close as possible to those achieved by ALD through the adjustment of PECVD process parameters. we conducted a total of nine PECVD processes, varying the process time and gas flow rates, which were identified as the most influential factors on the PECVD process. Furthermore, ellipsometry analysis was employed to examine the uniformity variations of each process. The experimental results enabled us to elucidate the relationship between uniformity and deposition rate, as well as the impact of gas flow rate and deposition time on the process outcomes. Additionally, thickness measurements obtained through ellipsometer facilitate the identification of optimal process parameters for PECVD.

Keywords

Acknowledgement

This paper was conducted with the support of the Korea Institute for Industrial Technology Promotion (G02P18800005502) through the 2024 Ministry Collaborative Semiconductor Major Track Project.

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