• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.6
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• pp.602-607
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• 2004

This paper describes the characteristics of Ru-Zr alloy gate electrodes deposited by co-sputtering. The various atomic composition was made possible by controlling sputtering power of Ru and Zr. Thermal stability was examined through 600 and 700 $^{\circ}C$ RTA annealing. Variation of oxide thickness and X-ray diffraction(XRD) pattern after annealing were employed to determine the reaction at interface. Low and relatively stable sheet resistances were observed for Ru-Zr alloy after annealing. Electrical properties of alloy film were measured from MOS capacitor and specific atomic composition of Zr and Ru was found to yield compatible work function for nMOS. Ru-Zr alloy was stable up to $700^{\circ}C$ while maintaining appropriate work function and oxide thickness.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1494-1495
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• 2009

Thin Film Transistor(TFT) having CIS (CuInSe) semiconductor layer was fabricated and characterized. Heavily doped Si was used as a common gate electrode and PECVD Silicon nitride ($SiN_x$) was used as a gate dielectric material for the TFT. Source and drain electrodes were deposited on the $SiN_x$ layer and CIS layer was formed by a direct patterning method between source and drain electrodes. Nanoparticle of CIS material was used as the ink of the direct patterning method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.7
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• pp.433-438
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• 2015

Zinc tin oxide transparent thin film transistors (ZTO TTFTs) were fabricated by using $n^+$ Si wafers as gate electrodes. Indium (In), aluminum (Al), indium tin oxide (ITO), silver (Ag), and gold (Au) were employed for source and drain electrodes, and the mobility and the threshold voltage of ZTO TTFTs were observed as a function of electrode. The ZTO TTFTs adopting In as electrodes showed the highest mobility and the lowest threshold voltage. It was shown that Ag and Au are not suitable for the electrodes of ZTO TTFTs. As the results of this study, it is considered that the interface properties of electrode/ZTO are more influential in the properties of ZTO TTFTs than the conductivity of electrode.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1312-1314
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• 2007

The effect of gate insulator surface treatment on electrical characteristics of bottom contact (BC) and suspended source/drain (SSD) organic thinfilm transistors (OTFTs) was studied. Triisopropylsilylethynyl pentacene was used as an active material and was printed by ink-jet printing method. In case of the BC OTFTs, threshold voltage was shifted from positive to near zero, and the fieldeffect mobility was increased when the gate insulator surface was treated with hexamethyldisilazane. However, in case of SSD OTFT, threshold voltage shift was not observed and the field-effect mobility was decreased.

• 한국초전도학회:학술대회논문집
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• v.11
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• pp.44-44
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• 2001

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.1
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• pp.23-26
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• 2017

Mo doped carbon (C:Mo) thin films were fabricated with various Mo target power densities by unbalanced magnetron sputtering (UBM). The effects of target power density on the surface, structural, and electrical properties of C:Mo films were investigated. UBM sputtered C:Mo thin films exhibited smooth and uniform surfaces. However, the rms surface roughness of C:Mo films were increased with the increase of target power density. Also, the resistivity value of C:Mo film as electrical properties was decreased with the increase of target power density. From the performance of organic thin filml transistor using conductive C:Mo gate electrode, the carrier mobility, threshold voltage, and on/off ratio of drain current (Ion/Ioff) showed $0.16cm^2/V{\cdot}s$, -6.0 V, and $7.7{\times}10^4$, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.12
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• pp.1140-1143
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• 2006

We report on the fabrication of P3HT-based thin-film transistors (TFTs) for liquid crystal display that consist of $NiO_x$, poly-vinyl phenol (PVP), and Ni for the source-drain (S/D) electrodes, gate dielectric layer, and gate electrode, respectively The $NiO_x$ S/D electrodes of which the work function is well matched to that of P3HT are deposited on a P3HT channel by electron-beam evaporation of NiO powder. The maximum saturation current of our P3HT-based TFT is about $15{\mu}A$ at a gate bias of -30 V showing a high field effect mobility of $0.079cm^2/Vs$ in the dark, and the on/off current ratio of our TFT is about $10^5$. It is concluded that jointly adopting $NiO_x$ for the S/D electrodes and PVP for gate dielectric realizes a high-quality P3HT-based TFT.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.395-395
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• 2007

We report on the fabrication of soluble pentacene-based thin-film transistors (TFTs) that consist of $NiO_x$, poly-vinyl phenol (PVP), and Ni for the source-drain (SID) electrodes, gate dielectric, and gate electrode, respectively. The $NiO_x$ SID electrodes of which the work function is well matched to that of soluble pentacene are deposited on a soluble pentacenechannel by sputter deposited of NiO powder and show a moderately low but still effective transmittance of ~65% in the visible range along with a good sheet resistance of ${\sim}40{\Omega}/{\square}$. The maximum saturation current of our soluble pentacene-based TFT is about $15{\mu}A$ at a gate bias of -40showing a high field effect mobility of $0.06cm^2/Vs$ in the dark, and the on/off current ratio of our TFT is about $10^4$. It is concluded that jointly adopting $NiO_x$ for the S/D electrodes and PVP for gate dielectric realizes a high-quality soluble pentacene-based TFT.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.83-90
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• 1986

A micro pH-ISFET probe, which can be applied to the in vivo measurements of the hydrogen ion concentration in blood, has been developed, and a measuring system equiped with this probe also developed. The pH-ISFET has been fatricated by employing the techniques of integrated circuit fabrication. Two kinds of micro electrode formed around the sensing gate during the wafer process, and the other is a capillary type of Ag/AfCl/sat. KCI reduced in size. This capillary electrode has shown its good performance characteristics so far in the application with ISFET as well as a commercial one. In order to form a micro pH-ISFET probe, this pH-ISFET and well as a commercial one. In order to form a micro pH-ISFET probe, this pH-ISFET and the capillary electrode were built together into a needle tip having 1 mm inner diameter. The chip size of a twin pH-ISFET is 0.8 mmx1.4 mm, the material of the sensing gate membrane is Si3N4, and the sensitivity of the developed probe is about 52mV/pH.