• 한국전기전자재료학회논문지
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• 제19권10호
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• pp.912-917
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• 2006

In this paper, Trench emitter electrode IGBT structure is proposed and studied numerically using the device simulator, MEDICI. The breakdown voltage, on-state voltage drop, latch up current density and turn-off time of the proposed structure are compared with those of the conventional trench gate IGBT(TIGBT) structures. Enhancement of the breakdown voltage by 19 % is obtained in the proposed structure due to dispersion of electric field at the edge of the bottom trench gate by trench emitter electrode. In addition, the on-state voltage drop and the latch up current density are improved by 25 %, 16 % respectively. However increase of turn-off time in proposed structures are negligible.

• 한국진공학회지
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• 제11권2호
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• pp.103-107
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• 2002

Metal/ferroelectric/semiconductor field effect transistors(MFSFET′s) with various gate electrodes, that are aluminum, platinum and poly-Si, using rapid thermal annealed $LiNbO_3$/Si(100) structures were fabricated and the properties of the FET′s have been discussed. The drain current of the "on" state of FET with Pt electrode was more than 3 orders of magnitude larger than the "off" state current at the same "read" gate voltage of 1.5 V, which means the memory operation of the MFSFET. A write voltage as low as about $\pm$4 V, which is applicable to low power integrated circuits, was used for polarization reversal. The retention properties of the FET using Al electrode were quite good up to about $10^3$ s and using Pt electrode remained almost the same value of its initial value over 2 days at room temperature.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.148-150
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• 2009

We have developed 15 inch, 130 blocks local dimming FEL using printed CNT emitters, in which multiple FE blocks were built with a common gate electrode. Cathode electrode formed by the double-metal technique, in which an insulator is interposed between the addressing bus and cathode electrode.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.25-28
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• 1999

Metal ferroelectric semiconductor Field Effect- Transistors(MFSFET) with various gate electrodes, that are aluminum, platinum and poly -Si, using LiNbO$_3$/Si(100) structures were fabricated and the properties of the FETs have been discussed. The drain current of the state of FET with Pt electrode was more than 3 orders of magnitude larger than the state current at the same gate voltage of 1.5 V, 7.rich means the memory operation of the MFSFET. A write voltage as low as about $\pm$4 V, which is applicable to low power integrated circuits, was used for polarization reversal. The retention properties of the FET using Al electrode were quite good up to about 10$^3$s and using Pt electrode remained almost the same value of its initial value over 2 days at room temperature.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.332.2-332.2
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• 2016

Two dimensional transition-metal dichalcogenides (TMDs) semiconductors are attractive materials for optoelectric devices because of their direct energy bandgap and transparency. To investigate the feasibility of transparent p-n junctions, we have fabricated a p-n heterojunction consisting of p-type WSe2 and n-type MoS2 flakes since WSe2 and MoS2 with proper electrode metals exhibit p-type and n-type behaviors, respectively. These heterojunctions exhibits gate-tunable rectifying behaviors and photovoltaic effects (ECE ~ 0.2%) indicating that p-n junctions were formed. In addition, photocurrent and photovoltaic effects were observed under light illumination, which were dependent on the gate voltage. In addition, the photocurrent mapping images indicate that the photovoltaic effects comes from the junction area. Possible origins of gate-tunability are discussed.

• 한국전기전자재료학회논문지
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• 제15권3호
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• pp.233-237
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• 2002

A giga-bit DRAM(dynamic random access memory) technology with W/WNx/poly-Si dual gate electrode is presented in 7his papers. We fabricated $0.16\mu\textrm{m}$ CMOS using this technology and succeeded in suppressing short-channel effects. The saturation current of nMOS and surface-channel pMOS(SC-pMOS) with a $0.16\mu\textrm{m}$ gate was observed 330 $\mu\A/\mu\textrm{m}$ and 100 $\mu\A/\mu\textrm{m}$ respectively. The lower salutation current of SC-pMOS is due to the p-doped poly gate depletion. SC-pMOS shows good DIBL(dram-induced harrier lowering) and sub-threshold characteristics, and there was no boron penetration.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1119-1122
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• 2005

A selective deposition of Co thin films for thin film transistor gate electrode has been carried out by the growth with combination of micro-contact printing and metal organic chemical vapor deposition (MOCVD). This results in the elimination of optical lithography process. MOCVD has been employed to selectively deposit Co films on preformed OTS gate pattern by using micro-contact printing (${\mu}CP$). A hydrogenated amorphous silicon TFT with a Co gate selectively formed on SAMs patterned structure exhibited a subthreshold slope of 0.88V/dec, and mobility of $0.35cm^2/V-s$, on/off current ratio of $10^6$, and a threshold voltage of 2.5V, and thus demonstrating the successful application of the novel bottom-up approach into the fabrication of a-Si:H TFTs.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.770-772
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• 2002

A new dry-processing method of organic gate dielectric film in field-effect transistors (FETs) was proposed. The method use vapor deposition polymerization (VDP) that is continuous and low temperature process. It has the advantages of shadow mask patterning and dry processing in flexible low-cost large area applications. Here, 80 nm-thick Al as a gate electrode was evaporated through shadow mask. Gate insulators used two different polyimides. The one material was 4,4'-oxydiphtahlic anhydride (ODPA) and 4,4'-oxydianiline (ODA). Another was 2,2-bis(3,4-dicarboxyphenyl) Hexafluoropropane Dianhydride (6FDA) and 4,4' -oxydianiline (ODA). These were co-deposited by high-vaccum thermal-evapora and cured at 150 $^{\circ}C$ for 1 hour, respectively. Pentacene as a semiconductor and 100 nm-thick Au as a source and drain electrode were evaporated through shadow mask.

• 조명전기설비학회논문지
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• 제16권1호
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• pp.13-19
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• 2002

새로운 방전 AND gate를 가지는 플라즈마 디스플레이 패널이 제안되었고 이를 검증하기 위한 구동 회로 시스템이 개발되었다. 그리고 방전 AND gate의 동작이 검증되었다. 방전 AND gate는 8$\mu\textrm{s}$의 동작속도와 20V의 동작마진을 가지고 동작하였으며 인근 주사라인의 방전을 정확히 제어할 수 있다는 것을 알았다. 이 방식은 직류 방전을 사용함으로 종래의 방전 AND gate에 비해 손쉽게 방전을 제어할 수가 있다. 더구나 AND gate의 입력방전과 출력방전이 분리되어 동작하기 때문에 디스플레이 방전이 AND gate를 통과하는 것을 방지할 수 있다. 그러므로 대화면 플라즈마 디스플레이에의 적용이 가능하고 주사방전이 화질에 영향을 주지 않으므로 명암비의 저하가 일어나지 않는다.