• Proceeding of EDISON Challenge
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• 2015.03a
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• pp.343-346
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• 2015

Ultra-thin body transistor is one of the emerging devices since it control leakage current flows through substrate. In addition, it can be operated by double gates, thus, its on/off current ratio is higher than conventional counterpart. In this paper, we design and investigate a CMOS inverter based on ultra-thin body MOSFETs to estimate its performance in real application. NEGF (non-equilibrium Green's function) method is used to obatain relationship between drain current and voltage. DC transfer is extracted from the relationship, and FO4 (fanout-of-4) propagation delay is reported as 5.1 ps estimated by a simple model.

• Proceedings of the IEEK Conference
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• summer
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• pp.70-73
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• 2004

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array (FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.657-658
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• 2006

A Novel level-shifter circuit for Display Panel Driver is presented. A Proposed level-shifter is for the high speed and high-voltage driving capability. In order to achieve this purpose, the proposed level-shifter restricts and separates the Vgs of the output driver's pull-up PMOS and pull-down NMOS with Zener diode. And a speed-up PMOS transistor is introduced to reduce delay. The control signal of speed-up PMOS was designed by bootstrapping method to minimize the gate to source (Vgs) voltage to avoid Vgs breakdown.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.786-793
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• 1987

This paper describes the design and fabrication of the polysilicon selfaligned bipolar transistor with 1.6\ulcorner epitaxy and SWAMI isolation technologies. This transistor has two levels of polysilicon. Also emitter and adjacent edge of polysilicon base contact of this PSA device are defined by the same mask, and emitter feature size is 2x4 \ulcorner. DC characteristic of the fabricated transistor was evaluated and analyzed for the SPICE input parameters. The minimum propagation delay time per gate of 330 ps at 1mW was obtained with 41 stage CML ring oscillator.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.1434-1444
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• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• Nuclear Engineering and Technology
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• v.55 no.9
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• pp.3334-3341
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• 2023

We studied the irradiation effects of fast neutron generated by a 30 MeV cyclotron on the electrical and switching characteristics of NPT-IGBT devices. Fast neutron fluence ranges from 2.7 × 10⁹ to 1.82 × 10¹³ n/cm². Electrical characteristics of the IGBT device such as I-V, forward voltage drop and additionally switching characteristics of turn-on and -off were measured. As the neutron fluence increased, the device's threshold voltage decreased, the forward voltage drop increased significantly, and the turn-on and turn-off time became faster. In particular, the delay time of turn-on switching was improved by about 35% to a maximum of about 39.68 ns, and that of turn-off switching was also reduced by about 40%-84.89 ns, showing a faster switching.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.741-746
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• 1986

A novel n-p-n bipolar transistor of which emitter is self-aligned with base contact by polyilicon is developed for using in high speed and high packing density LSI circuits. The emitter of this transistor is separated less than 0.4 \ulcorner with base contact by self-aligh technology, and the emitter feature size is less than 3x5 \ulcorner\ulcorner Because the active region of this transistor is not damaged through all the process, it has excellent electric properties. Using the n-p-n transistors by 3.0\ulcorner design rules, a NTL ring oscillator has 380 ps, a CML ring oscillator has 390ps, and a I\ulcorner ring oscillator has 5.6ns of per-gate minimum propagation delay time.

• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.147-151
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• 2024

The importance of Wireless Sensor Networks is becoming more evident owing to their practical applications in various areas. However, the energy problem remains a critical barrier to the progress of WSNs. By reducing the energy consumed by the sensor nodes that constitute WSNs, the performance and lifespan of WSNs will be enhanced. In this study, we introduce an energy-efficient ternary modulator that employs multi-threshold CMOS for logic conversion. We optimized the design with a low-power ternary gate structure based on a pass transistor using the MTCMOS process. Our design uses 71.69% fewer transistors compared to the previous design. To demonstrate the improvements in our design, we conducted the HSPICE simulation using a CMOS 180 nm process with a 1.8V supply voltage. The simulation results show that the proposed ternary modulator is more energy-efficient than the previous modulator. Power-delay product, a benchmark for energy efficiency, is reduced by 97.19%. Furthermore, corner simulations demonstrate that our modulator is stable against PVT variations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.

• Nuclear Engineering and Technology
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• v.21 no.4
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• pp.287-293
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• 1989

The purpose of this study was to develop a rapid and effective method of laser-induced fluorescence analysis for thrace amounts of Sm, Eu and Tb in nuclear fuels. The features of the method are the use of the distinct fluorescence wavelengths and the discriminative lifetimes of the respective elements when excited by a pulsed nitrogen laser. Fluorescence signals of the three elements were isolated by adequate selection of the filters or complexing agents (HFA, TTA) or discriminative delay and gate times in the signal processing circuit. It was found that S $m^{+3}$ and E $u^{+3}$ emitted strong fluorescence in the two complexing agent solutions or HFA and TTA. But in the case or T $b^{+3}$, the fluorescence signal was detected only in HFA solution. With respect to the concentrations of S $m^{+3}$, E $u^{+3}$ and T $b^{+3}$, the fluorescence signal intensities gave superior linearities in the range of 5 ppb-10 ppm for S $m^{+3}$, 0.5 ppb-1 ppm for E $u^{+3}$, and 0.1 ppb-300 ppb for T $b^{+3}$, The detection limits obtained were 5 ppb for S $m^{+3}$, 0.1 ppb for E $u^{+3}$, and 0.01 ppb for T $b^{+3}$, respectively.