• 제목/요약/키워드: gate condition

검색결과 327건 처리시간 0.031초

P-채널 MOSFET에서 게이트와 기판 전류의 시간에 따른 복원 특성 (Restoration Characteristics along to Time of the Gate and Substrate Current in p-channel MOSFETS)

  • 조상운;장원수;배지철;이용재
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
    • /
    • pp.1101-1104
    • /
    • 2003
  • In this paper, we analyzed the gate current and substrate current by the hot carrier effects and restoration phenomenon of characteristics by time in the p-channel MOSFETs. The Stress voltage condition is a voltage in maximum gate current and time is 3s, 10s, 30s, l00s, 1000s, 2000s and 3000s. As results of analysis, the gate current and substrate current were decreased by stress time, and the restoration time of characteristics were shown the results that were decreased by the exponential times.

  • PDF

Characterization of Thin Film Transistor using $Ta_2O_5$ Gate Dielectric

  • Um, Myung-Yoon;Lee, Seok-Kiu;Kim, Hyeong-Joon
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
    • /
    • pp.157-158
    • /
    • 2000
  • In this study, to get the larger drain current of the device under the same operation condition as the conventional gate dielectric SiNx thin film transistor devices, we introduced new gate dielectric $Ta_2O_5$ thin film which has high dielectric constant $({\sim}25)$ and good electrical reliabilities. For the application for the TFT device, we fabricated the $Ta_2O_5$ gate dielectric TFT on the low-temperature-transformed polycrystalline silicon thin film using the self-aligned implantation processing technology for source/drain and gate doping. The $Ta_2O_5$ gate dielectric TFT showed better electrical performance than SiNx gate dielectric TFT because of the higher dielectric constant.

  • PDF

장시간 스트레스 조건에서 submicron MOSFET의 열전자 트래핑에 의한 노화현상에 대한 연구 (A study on the degradation by the hot carrier trapping of the submicron MOSFET with long stress condition)

  • 홍순석
    • E2M - 전기 전자와 첨단 소재
    • /
    • 제8권3호
    • /
    • pp.357-361
    • /
    • 1995
  • An experiment on characteristics of nMOSFET's in the long stress condition with the maximum of the substrate current has been carried out in order to study on the degradation due to the hot-carrier effect. Based on the measured result of the threshold voltage, the damage is mostly due to the hole injection into the oxide. After long stress, it was shown that the drain current increased at low gate voltages and hence decreased at high gate voltages.

  • PDF

COMMON FIXED POINTS FOR SINGLE-VALUED AND MULTI-VALUED MAPPINGS IN COMPLETE ℝ-TREES

  • Phuengrattana, Withun;Sopha, Sirichai
    • 대한수학회논문집
    • /
    • 제31권3호
    • /
    • pp.507-518
    • /
    • 2016
  • The aim of this paper is to prove some strong convergence theorems for the modified Ishikawa iteration process involving a pair of a generalized asymptotically nonexpansive single-valued mapping and a quasi-nonexpansive multi-valued mapping in the framework of $\mathbb{R}$-trees under the gate condition.

N-Input NAND Gate에서 입력조건에 따른 Voltage Transfer Function에 관한 연구 (A Study of The Voltage Transfer Function Dependent On Input Conditions For An N-Input NAND Gate)

  • 김인모;송상헌;김수원
    • 대한전기학회논문지:전기물성ㆍ응용부문C
    • /
    • 제53권10호
    • /
    • pp.510-514
    • /
    • 2004
  • In this paper, we analytically examine the voltage transfer function dependent on input conditions for an N-Input NAND Gate. The logic threshold voltage, defined as a voltage at which the input and the output voltage become equal, changes as the input condition changes for a static NAND Gate. The logic threshold voltage has the highest value when all the N-inputs undergo transitions and it has the lowest value when only the last input connected to the last NMOS to ground, makes a transition. This logic threshold voltage difference increases as the number of inputs increases. Therefore, in order to provide a near symmetric voltage transfer function, a multistage N-Input Gate consisting of 2-Input Logic Gates is desirable over a conventional N-Input Gate.

A Study on the Stem Coefficient of Friction of Motor- operated Gate/Globe halves

  • Jeoung, Rae-Hyuck;Park, Sung-Keun;Lee, Do-Hwan;Kim, Yang-Seok
    • Nuclear Engineering and Technology
    • /
    • 제35권2호
    • /
    • pp.133-143
    • /
    • 2003
  • Stem-stem nut coefficient of friction(COF) in motor-operated gate/globe valves is one of the important factors which determine the performance of the valve/actuators. The COF is affected greatly by the type and condition of the stem-stem nut lubricants, environmental parameters, surface condition of the stem/stem-nuts, and the number of strokes after the lubrication. In this paper, the measured data of the COFs at stem threads of some safety-related motor-operated gate/globe valves in domestic nuclear power plants are presented. In addition, the performance of the lubricants is evaluated by comparing the COFs among those valves. The results show that the measured COF at torque switch trip are higher than the unwedging COF and conservatively applicable to the unwedging COF. It is also shown that the lubricating performance based on the measured COFs varies with the lubricants.

EL 구동용 공진형 인버터 특성에 관한 연구 (A Study on the Characteristic for EL Driving Resonant Inverter)

  • 윤석암
    • 전력전자학회:학술대회논문집
    • /
    • 전력전자학회 2000년도 전력전자학술대회 논문집
    • /
    • pp.380-383
    • /
    • 2000
  • This paper presents about EL(electro-luminescent) driver with inverter Inverter is constructed by using characteristic of FET and its output characteristics is analysed for the variation of gate bias frequency and load. The optimum operating condition of inverter is that the gate bias frequency of FET equal two resonant frequency of circuit.

  • PDF

Harbor Gate와 유입하천의 영향을 고려한 만내의 2차원 수리해석 (A Two-dimensional Hydraulic Analysis Considering the Influence of River Inflow and Harbor Gate in the Bay)

  • 이재준;이후상;심재설;윤종주
    • 한국수자원학회논문집
    • /
    • 제48권1호
    • /
    • pp.45-55
    • /
    • 2015
  • 본 연구에서는 연안지역의 방재를 위하여 외해에 방조제를 설치하였을 때 유입하천의 홍수량을 고려하여 만내의 2차원 수리분석을 실시하였다. 대상지역으로 영산강과 목포항 해역을 선정하였으며, 먼저 영산강 살리기 사업으로 인한 하상준설 및 하도변화에 따른 영산강의 수위영향을 검토하기 위하여 HEC-RAS 모형을 적용하여 1차원수리분석을 실시하였다. 또한, 전세계적으로 사용되고 범용 및 상용화 되어있는 2차원 동수역학 모형인 SMS의 CMS-Flow 모델을 이용하여 외해에 Harbor Gate 설치를 통한 2차원 수리분석을 하고, 영산강의 홍수량에 대한 수리학적 흐름의 특성을 분석함으로써 2차원 모형의 적합성을 검토하였다. 2차원 수리분석은 방조수문 설치 유 무와 내수경계조건으로 영산강 유입량 적용 유무을 고려한 4가지 경우에 대하여 외해 경계조건을 부여하여 실시하였으며, 2차원 모형의 적용 결과 방조수문 설치로 인하여 목포항 해역의 해수면 변화는 영산강 하구둑의 방류량이 지배적이며, 방조수문과 하구둑에 의해 만들어진 저수지의 용적량이 방류량의 용적에 비해 많이 부족하므로 방조수문 설치시 영산강 하구둑과 방조수문의 유기적인 운영이 필요하다고 판단된다.

Threshold Voltage Dependence on Bias for FinFET using Analytical Potential Model

  • Jung, Hak-Kee
    • Journal of information and communication convergence engineering
    • /
    • 제8권1호
    • /
    • pp.107-111
    • /
    • 2010
  • This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.