• 한국컴퓨터산업교육학회:학술대회논문집
• /
• 2003.11a
• /
• pp.67-70
• /
• 2003

In this paper, propose a new structure of MOFET(Metal-Oxide-Semiconductor Field Effect Transistor) which is widely application for semiconductor technologies. Eleminate the latch-up effect caused by closed devices when conpose a electronic circuit using proposed devices. In this device have a completely isolation structure, and advantage of leakage current elimination. Each independent devices are isolated by trench-well and oxide layer of SOI substrate. Using trench gate and self aligned techniques reduces parasitic capacitance between gate and source, drain. In this paper, we proposed the new structure of SOI MOSFET which has completely isolation and contains trench gate electrodes and SOI wafers. It is simulated by MEDICI that is device simulator.

• Journal of Sensor Science and Technology
• /
• v.24 no.3
• /
• pp.165-168
• /
• 2015

We demonstrated low-voltage organic thin-film transistors (OTFTs) with bilayer insulators, high-k polymer and low temperature crosslinkable polymer, on a flexible plastic substrate. Poly (vinylidene fluoridetrifluoroethylene) (P(VDF-TrFE)) and poly (2-vinylnaphthalene) are used for high-k polymer gate insulator and low temperature crosslinkable polymer insulators, respectively. The mobility of flexible OTFTs is $0.17cm^2/Vs$ at gate voltages -5 V after bending operation.

• Journal of the Semiconductor & Display Technology
• /
• v.13 no.4
• /
• pp.55-58
• /
• 2014

The next-generation AlGaN/GaN HEMT power devices need higher power at higher frequencies. To know the device characteristics, the simulation of those devices are made. This paper presents a simulation study on the DC and RF characteristics of AlGaN/GaN HEMT power devices. According to the reduction of gate length from $2.0{\mu}m$ to $0.1{\mu}m$, the simulation results show that the drain current at zero gate voltage increases, the gate capacitance decreases, and the maximum transconductance increases, and thus the cutoff frequency and the maximum oscillation frequency increase. The maximum oscillation frequency maintains higher than the cutoff frequency, which means that the devices are useful for power devices at very high frequencies.

• Journal of the Korean institute of surface engineering
• /
• v.33 no.4
• /
• pp.217-221
• /
• 2000

The gate oxide thickness is becoming thinner and thinner in order to speed up the semiconductor CMOS devices. We have investigated very thin$ SiO_2$ gate oxide layers and found anomaly between the thickness determined with capacitance measurement and these obtained with cross-sectional high resolution transmission electron microscopy. The thicknesses difference of the two becomes important for the thickness of the oxide below 5nm. We propose that the variation of dielectric constant in thin oxide films cause the anomaly. We modeled the behavior as (equation omitted) and determined $\varepsilon_{bulk}$=3.9 and $\varepsilon_{int}$=-4.0. We predict that optimum $SiO_2$ gate oxide thickness may be $20\AA$ due to negative contribution of the interface dielectric constant. These new results have very important implication for designing the CMOS devices.s.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.37 no.1
• /
• pp.48-55
• /
• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.4
• /
• pp.35-42
• /
• 2013

In this paper, the analog performance of FinFET structure was estimated by extracting the DC/AC characteristics of the 22 nm process FinFET structures with different layout considering spacer and SEG using 3D device simulator, Sentaurus. Based on the analysis results, layout methods to enhance the analog performance of multi-fin FinFET structures are proposed. By adding the spacer and SEG structures, the drive current of 1-fin FinFET increases. However, the unity gain frequency, $f_T$, reduces by 19.4 % due to the increase in the total capacitance caused by the added spacer. If the process element is not included in multi-fin FinFET, replacing 1-finger with 2-finger structure brings approximately 10 % of analog performance improvement. Considering the process factors, we propose methods to maximize the analog performance by optimizing the interconnect and gate structures.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.7
• /
• pp.39-46
• /
• 2009

A fast-switching current-pulse driver for light emitting diode (LED) backlight is proposed. It uses a regulated drain current mirror (RD-CM) [1] and a high-voltage NMOS transistor (HV-NMOS). It achieves the fast-response current-pulse switching by using a dynamic gain-boosting amplifier (DGB-AMP). The DGB-AMP does not discharge the large HV-NMOS gate capacitance of the RD-CM when the output current switch turns off. Therefore, it does not need to charge the HV-NMOS gate capacitance when the switch turns on. The proposed current-pulse driver achieves the fast current switching by removing the repetitive gate discharging and charging. Simulation results were verified with measurements performed on a fabricated chip using a 5V/40V 0.5um BCD process. It reduces the switching delay to 360ns from 700ns of the conventional current-pulse driver.

• Journal of the Microelectronics and Packaging Society
• /
• v.14 no.1
• /
• pp.27-31
• /
• 2007

The cpapcitors with MIM(metal-insulator-metal) structures using PVP gate insulation films were prepared for the application of flexible organic thin film transistors (OTFT). The co-polymer organic insulation films were synthesized by using PVP(poly-4-vinylphenol) as a solute and PGMEA(propylene glycol monomethyl ether acetate) as a solvent. The cross-linked PVP insulation films were also prepared by addition of poly(melamine-co-formaldehyde) as thermal hardener. The leakage current of the cross- linked PVP films was found to be about 1.3 nA on Al/PES(polyethersulfone) substrate, whereas, on ITO/ glass substrate was about 27.5 nA indicating improvement of the leakage current at Al/PES substrates. Also, the capacitances of all prepared samples on ITO/glass and Al/PES substrates w ere ranged from 1.0 to $1.2nF/cm^2$, showing very similar result with the calculated capacitance values.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.3
• /
• pp.196-208
• /
• 2007

An analytical model is proposed for an optically controlled Metal Semiconductor Field Effect Transistor (MESFET), known as Optical Field Effect Transistor (OPFET) considering the diffusion fabrication process. The electrical parameters such as threshold voltage, drain-source current, gate capacitances and switching response have been determined for the dark and various illuminated conditions. The Photovoltaic effect due to photogenerated carriers under illumination is shown to modulate the channel cross-section, which in turn significantly changes the threshold voltage, drainsource current, the gate capacitances and the device switching speed. The threshold voltage $V_T$ is reduced under optical illumination condition, which leads the device to change the device property from enhancement mode to depletion mode depending on photon impurity flux density. The resulting I-V characteristics show that the drain-source current IDS for different gate-source voltage $V_{gs}$ is significantly increased with optical illumination for photon flux densities of ${\Phi}=10^{15}\;and\;10^{17}/cm^2s$ compared to the dark condition. Further more, the drain-source current as a function of drain-source voltage $V_{DS}$ is evaluated to find the I-V characteristics for various pinch-off voltages $V_P$ for optimization of impurity flux density $Q_{Diff}$ by diffusion process. The resulting I-V characteristics also show that the diffusion process introduces less process-induced damage compared to ion implantation, which suffers from current reduction due to a large number of defects introduced by the ion implantation process. Further the results show significant increase in gate-source capacitance $C_{gs}$ and gate-drain capacitance $C_{gd}$ for optical illuminations, where the photo-induced voltage has a significant role on gate capacitances. The switching time ${\tau}$ of the OPFET device is computed for dark and illumination conditions. The switching time ${\tau}$ is greatly reduced by optical illumination and is also a function of device active layer thickness and corresponding impurity flux density $Q_{Diff}$. Thus it is shown that the diffusion process shows great potential for improvement of optoelectronic devices in quantum efficiency and other performance areas.

• Proceedings of the Korea Crystallographic Association Conference
• /
• 2002.11a
• /
• pp.42-43
• /
• 2002

반도체 디바이스의 발전은 높은 직접화 및 동작 속도를 추구하고 있으며, 이를 위해서 MOSFET의 scale down시 발생되는 문제를 해결해야만 한다. 특히, Channel이 짧아짐으로써 발생하는 device의 열화현상으로 동작전압의 조절이 어려워 짐을 해결해야만 하며, gate oxide 두께를 줄임으로써 억제할 수 있다고 알려져 왔다. 현재, gate oxide으로 사용되고 있는 SiO2박막은 비정질로써 ～8.7 eV의 높은 band gap과 Si기판 위에서 성장이 용이하며 안정하다는 장점이 있으나, 두께가 1.6 nm 이하로 얇아질 경우 전자의 direct Tunneling에 의한 leakage current 증가와 gate impurity인 Boron의 channel로의 확산, 그리고 poly Si gate의 depletion effect[1,2] 등의 문제점으로 더 이상 사용할 수 없게 된다. 2001년 ITRS에 의하면 ASIC제품의 경우 2004년부터 0.9～l.4 nm 이하의 EOT가 요구된다고 발표하였다. 따라서, gate oxide의 물리적인 두께를 증가시켜 전자의 Tunneling을 억제하는 동시에 유전막에 걸리는 capacitance를 크게 할 수 있다는 측면에서 high-k 재료를 적용하기 위한 연구가 진행되고 있다[3]. High-k 재료로 가능성 있는 절연체들로는 A1₂O₃, Y₂O₃, CeO₂, Ta₂O, TiO₂, HfO₂, ZrO₂,STO 그리고 BST등이 있으며, 이들 재료 중 gate oxide에 적용하기 위해 크게 두 가지 측면에서 고려해야 하는데, 첫째, Si과 열역학적으로 안정하여 후속 열처리 공정에서 계면층 형성을 배제하여야 하며 둘째, 일반적으로 high-k 재료들은 유전상수에 반비례하는 band gap을 갖는 것으로 알려줘 있는데 이 Barrier Height에 지수적으로 의존하는 leakage current때문에 절연체의 band gap이 낮아서는 안 된다는 점이다. 최근 20이상의 유전상수와 ～5 eV 이상의 Band Gap을 가지며 Si기판과 열역학적으로 안정한 ZrO₂[4], HfiO₂[5]가 관심을 끌고 있다. HfO₂은 ～30의 고유전상수, ～5.7 eV의 높은 band gap, 실리콘 기판과의 열역학적 안전성 그리고 poly-Si와 호환성등의 장점으로 최근 많이 연구가 진행되고 있다. 또한, Hf은 SiO₂를 환원시켜 HfO₂가 될 수 있으며, 다른 silicide와 다르게 Hf silicide는 쉽게 산화될 수 있는 점이 보고되고 있다.