• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.56-62
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• 1999

All the cells on the whole memory array or a block of the memory array in the Flash EEPROM's are erased at the same time using Fowler-Nordheim (FN) tunneling. some of the cels are often overerased since the tunneling is not a self-limited process. In this paper, the optimum doping concentration of the floating gate solve the overerase problem has been studied. For these studies, N-type MOSFETs and MOS capacitors with various doping concentrations of the gate polysilicon have been fabricated and their electrical characteristics have been measured and analyzed. As the results of the experiment, it has been found that the overerase problem can be prevented if the doping concentration of the floating gate is low enough (i.e. below $1.3{\times}10^{18}/cm^3$). It is because the potential difference between the floating gate and the source is lowered due to the formation of the depletion layer in the floating gate and thus the erasing operation stops by itself after most of the electrons stored in the floating gate are extracted. On the other hand, the uniformity of the Vt and the gm has been significantly poor if the coping concentration of the floating, gate is too much lowered (i.e. below $1.3{\times}10^{17}/cm^3$), which is believed to be due to nonuniform loss of the dopants from the nonuniform segregation in the floating gate. Consequently, the optimum doping concentration of the floating gate to suppress the overerase problem and get the uniform Vt and has been found to range from $1.3{\times}10^{17}/cm^3$ to $1.3{\times}10^{18}/cm^3$ in the Flash EEPROM.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.74.2-74
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• 2002

$\textbullet$ Roll Control $\textbullet$ Switched Reluctance Motor $\textbullet$ Field Programmable Gate Array $\textbullet$ Single Pulse Mode Current Control $\textbullet$ OR/Off Angle Control

• Proceedings of the Optical Society of Korea Conference
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• 2007.02a
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• pp.84-85
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• 2007

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.67-88
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• 2005

Mold-Flow 3 Die Stack CSP of Mold array packaging with different Gate types. As high density package option such as 3 or 4 die stacking technologies are developed, the major concerning points of mold related qualities such as incomplete mold, exposed wires and wire sweeping issues are increased because of its narrow space between die top and mold surface and higher wiring density. Full 3D rheokinetic simulation of Mold flow for 3 die stacking structure case was done with the rheological parameters acquired from Slit-Die rheometer and DSC of commercial EMC. The center gate showed severe void but corner gate showed relatively better void performance. But in case of wire sweeping related, the center gate type showed less wire sweeping than corner gate types. From the simulation results, corner gate types showed increased velocity, shear stress and mold pressure near the gate and final filling zone. The experimental Case study and the Mold flow simulation showed good agreement on the mold void and wire sweeping related prediction. Full 3D simulation methodologies with proper rheokinetic material characterization by thermal and rheological instruments enable the prediction of micro-scale mold filling behavior in the multi die stacking and other complicated packaging structures for the future application.

• Journal of the Korean Society of Radiology
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• v.13 no.4
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• pp.661-666
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• 2019

Diverging collimators is used to obtain reduced images of an object, or to detect a wide filed-of-view (FOV) using a small gamma camera. In the gamma camera using the diverging collimators, the block scintillator, and the pixel scintillator array, gamma rays are obliquely incident on the scintillator surface when the source is located the periphery of the FOV. Therefore, the spatial resolution is reduced because it is obliquely detected in depth direction. In this study, we designed a novel system to improve the spatial resolution in the periphery of the FOV. Using a tapered crystal array to configure the scintillation pixels to coincide with the angle of the collimator's hole allows imaging to one scintillation pixel location, even if events occur to different depths. That is, even if is detected at various points in the diagonal direction, the gamma rays interact with one crystal pixel, so resolution does not degrade. The resolution of the block scintillator and the tapered crystal array was compared and evaluated through Geant4 Application for Tomographic Emission (GATE) simulation. The spatial resolution of the obtained image was 4.05 mm in the block scintillator and 2.97 mm in the tapered crystal array. There was a 26.67% spatial resolution improvement in the tapered crystal array compared to the block scintillation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.30-37
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• 1998

An analog array with a 1.2 $\mu\textrm{m}$ double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.10
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• pp.532-535
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• 2001

The sputtering condition of Cr thin film was established in order to get Cr gate electrode having a vertical wall structure for Mo-tip FEA. In case of Mo-tip FEA which had a vertically-etched Cr gate electrode, the field enhancement factor, was relatively increased and so the field emission performance in terms of turn-on voltage, emission current and trans-conductance could be improved when compared with the devices having a tapered gate wall.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.822-828
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• 2019

An Augmented Reality(AR) provides virtual information with a real environment, and the processor needs to access the memory for the AR system. However, the processor has the heavy workload as the technology improvement leads to increase the size of data. We need a specific module to reduce the workload to overcome the limitation. In this paper, we propose a Direct Memory Access(DMA) controller displaying image instead of the processor. We implemented the proposed DMA controller on a Field Programmable Gate Array(FPGA) and demonstrated the functionality of the DMA controller based on an Avalon Memory Mapped(Avalon-MM) interface. Also, the DMA controller is fabricated by using Magnachip/Hynix 0.35um CMOS technology and verified the feasibility of the embedded system.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.11a
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• pp.388-389
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• 2022

Recently, AI (Artificial Intelligence) has been applied to various technologies such as automatic driving, robot and smart communication. Currently, AI system is developed by software-based method using tensor flow, and GPU (Graphic Processing Unit) is employed for processing unit. However, if software-based method employing GPU is used for AI applications, there is a problem that we can not change the internal circuit of processing unit. In this method, if high-level jobs are required for AI system, we need high-performance GPU, therefore, we have to change GPU or graphic card to perform the jobs. In this work, we developed a CNN-based FPGA (Field Programmable Gate Array) chip to solve this problem.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.1-8
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• 1990

We made a 12-Laser Diode Array consisting of 12 Graded Index Separate Confinement (GRINSCH) InGaAs/Inp Buried Heterostructure 4 Quantum Well Laser Diodes and examined the potential of controlling lasing operation of each laser diode by the voltage to its electroabsorption region. Using Si V-Groove with 12 V-grooves, a 12-Laser Diode Array, and 12 optical fibers, we investigated the various characteristics of each laser diode by changing the voltage to its electro-absorption region. Finally, we thought over the promising way of implementing optical local area communication between electric circuit boards or between subscribers and a central office using a 12-Laser Diode Array, Si V-groove, and optical fibers.