• 제어로봇시스템학회:학술대회논문집
• /
• 2002.10a
• /
• pp.89.4-89
• /
• 2002

$\textbullet$ Field Programmable Gate Array $\textbullet$ flexible hardware $\textbullet$ neural network $\textbullet$ determinism learning $\textbullet$ multi-valued logic $\textbullet$ disjunctive normal form $\textbullet$ multi-dimensional exclusive OR

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2006.10a
• /
• pp.65-66
• /
• 2006

• The Magazine of the IEIE
• /
• v.31 no.8
• /
• pp.44-51
• /
• 2004

최근 SoC (System on Chip) 기술의 발전으로 최대 10 Gbps의 처리율을 갖는 네트워크 프로세서가 개발되고 있다. 네트워크 프로세서는 기존의 ASIC (Application Specific Integrated circuit)또는 FPGA (Field Programmable Gate Array) 등 하드웨어가 수행하던 고속의 패킷 처리 기능을 소프트웨어 기반으로 처리하도록 함으로써 다양한 기능의 패킷 처리를 저비용으로 단시간 내에 개발 할 수 있는 장점을 갖고 있다.(중략)

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2007.06a
• /
• pp.59-60
• /
• 2007

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 1984.10a
• /
• pp.25-27
• /
• 1984

Using LED sources, the system that performs optical logic function of the input data arrays will be presented. Sixteen possible functions of two binary data arrays, such as AND, OR, NOR and XOR are simply obtained in parallel by controlling LED switching mode. Experimental result and some examples of application will be given.

• The Magazine of the IEIE
• /
• v.19 no.6
• /
• pp.55-60
• /
• 1992

본 논문은 ISDN U-interface 회로 중에서 digital 부분의 설계에 대하여 기술하였다. 이 회로는 MMS43 code와 echo cancellation 방식을 사용하여 구현되었다. 회로 구성상 interface부분과 DSP부분으로 나누어 설계하였으며 gate-array ASIC을 이용하여 chip을 제작하였다. 공정은 1um CMOS 기술을 사용하였다.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.352-354
• /
• 2008

A 15.4" WXGA TFT-LCD, featuring integrated a-Si:H gate driver circuits and reduced data driver ICs, has been developed. To reduce number of data lines into 1/2 of conventional structure, the pixel array has been re-mapped with re-organized data signal. Unintended artificial effects such as flicker were removed by adopting the novel pixel array having a 'zigzag' map. To minimize the power consumption, a column inversion method was incorporated in the zigzag pixel array (Fig.1) without modifying the polarity map of conventional dot inversion method.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.1568-1570
• /
• 2008

In this paper, fabrication of a $60{\times}48$ polymer TFT array with a top-gate structure on plastic substrates using a low temperature printing process will be presented and the device structure and manufacturing processes will be discussed. The polymer TFT array showed excellent air stability and uniform electrical characteristics over a large area. Finally, a 1.5 inch EPD display with 50 dpi resolution using the polymer TFT array will be demonstrated for e-film device applications.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.9 no.1
• /
• pp.95-102
• /
• 2013

This paper covers nulling algorithm. In this algorithm, we assume that nulling points are already known. In general, nulling algorithm using matrix equation was utilized. But, this algorithm is pointed out that computational complexity is disadvantage. So, we choose gradient method to reduce the computational complexity. In order to further reduce the computational complexity, we propose approximate gradient method using characteristic of trigonometric functions. The proposed method has same performance compared with conventional method while having half the amount of computation when the number of antenna and nulling point are 20 and 1, respectively. In addition, we could virtually eliminate the trigonometric functions arithmetic. Trigonometric functions arithmetic cause a big problem in actual implementation like FPGA processor(Field Programmable gate array). By utilizing the above algorithm in a multi-cell environment, beamforming gain can be obtained and interference can be reduced at same time. By the above results, the algorithm can show excellent performance in the cell boundary.

• Journal of Korea Society of Industrial Information Systems
• /
• v.18 no.5
• /
• pp.45-50
• /
• 2013

Recently, as the market for SMART TV expands, the camera is embedded for providing various user experience. However, this leads to occurrence of camera failure due to TV power up sequence problem, which are usually not detectable in conventional test equipments. Although the failure-detection can be possible by re-generating control signals for audio interface with new equipment, it is expensive and also requires much time to test. In this paper, for SMART TV, FPGA(Field Programmable Gate Array)-based failure-detection system is proposed which can lead to reduction of both cost and time for test.