• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.16-22
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• 1994

In this paper, transmitter and receiver modules for free space optical interconnection are implemented and characterized. In the transmitter module, bias circuitry which inject current into the direct modulated laser diode is fabricated and in the receiver module, p-i-n diode is integrated with an MMIC amplifying stage. Laser diode has a direct-modulated bandwidth of 2 GHz at 1.4 Ith bias while p-i-n diode and amplifying stage has a bandwidth of 1.3 GHz and 1.5 GHz, repectively. Optical interconnection has a bandwidth of 1.3 GHz and linearly transmit modulated voltage signal up to 1.5 Vp-p. Measured loss of optical interconnection is 5dB which is composed of optoelectronic conversion loss of 15 dB, electrical impedance mismatch loss of 6.7 dB in transmitter module and gain of 18 dB in receiver module. Seperation between transmitter and receiver can be extended up to 50 cm by using a lens.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.37 no.5
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• pp.319-326
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• 1988

In the presence of unmodeled dynamics, the robustness of adaptive pole assignment control using new pseudo-plant is presented. The pseudo-plant proposed by Donati et al. is modified as the gain of low pass filter can be set from zero to one. This modified pseudo-plant results in the reduction of modeling error. It is shown that not only this approach is insensitive to input frequency but also it improves the conic condition developed by Ortega et al. which is required to assure stability of adaptive control system despite the model-plant mismatch. A simple method to compensate the tracking error due to the use of pseudo-plant is considered.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.9
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• pp.44-50
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• 2002

Recently, a envelope tracking(ET) amplifier that improves efficiency by changing of the bias according to the RF input level is presented to use for a high power amplifier of cellular radio handset using CDMA. The input and the output impedances of the ET amplifier may be varied by changing of the bias of the amplifier, and it makes the amplifier having low gain, low efficiency, and high input and output VSWR. In order to improve the input and the output mismatch of the amplifier, in this paper, two types of ET amplifier are suggested. In case of an ET amplifier using varactor diode, in experimentation, gain is improved about 7dB and the power consumption of the amplifier is better about 60% than that of the conventional amplifier. In case of a base voltage controlled ET amplifier, the gain and power consumption of the amplifier is improved about 9dB and 40% than those of the conventional amplifier, respectively.

• Journal of electromagnetic engineering and science
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• v.18 no.3
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• pp.188-198
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• 2018

In this study, we propose an approach for the design and satisfy the requirements of the fabrication of a small, lightweight, reliable, and stable ultra-wideband receiver for millimeter-wave bands and the contents of the approach. In this paper, we designed and fabricated a stable receiver with having low noise figure, flat gain characteristics, and low noise characteristics, suitable for millimeter-wave bands. The method uses the chip-and-wire process for the assembly and operation of a bare MMIC device. In order to compensate for the mismatch between the components used in the receiver, an amplifier, mixer, multiplier, and filter suitable for wideband frequency characteristics were designed and applied to the receiver. To improve the low frequency and narrow bandwidth of existing products, mathematical modeling of the wideband receiver was performed and based on this spurious signals generated from complex local oscillation signals were designed so as not to affect the RF path. In the ultra-wideband receiver, the gain was between 22.2 dB and 28.5 dB at Band A (input frequency, 18-26 GHz) with a flatness of approximately 6.3 dB, while the gain was between 21.9 dB and 26.0 dB at Band B (input frequency, 26-40 GHz) with a flatness of approximately 4.1 dB. The measured value of the noise figure at Band A was 7.92 dB and the maximum value of noise figure, measured at Band B was 8.58 dB. The leakage signal of the local oscillator (LO) was -97.3 dBm and -90 dBm at the 33 GHz and 44 GHz path, respectively. Measurement was made at the 15 GHz IF output of band A (LO, 33 GHz) and the suppression characteristic obtained through the measurement was approximately 30 dBc.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1310-1318
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• 1998

Sigma-delta converter is frequently used for conyerting low-frequency anglog to digital signal. The converter consists of a modulator and a digital filer, but our work is concentrated on the modulator. In this works, to design second-order sigma-dalta modulator with 14bit resolution, we define maximumerror limits of each components (operational smplifier, integrator, internal ADC, and DAC) of modulator. It is first performed modeling of an ideal second-order sigma-delta modulator. This is then modified by adding the non-ideal factors such as limit of op-amp output swing, the finit DC gain of op-amp slew rate, the integrator gian error by the capacitor mismatch, the ADC error by the cmparator offset and the mismatch of resistor string, and the non-linear of DAC. From this modeling, as it is determined the specification of each devices requeired in design and the fabrication error limits, we can see the final performance of modulator.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.261-269
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• 2013

In this paper, the evoked potential(EP) was represented by additive delay model to comply with the variational noisy response of stimulus-event synchronization. The hybrid method of delay compensated-Wiener filtered-ensemble averaging(DWEA) was proposed to enhance the EP signal distortion occurred during averaging procedure due to synchronization timing mismatch. The performance of DWEA has been tested by surrogated simulation, which is composed of synthesized arbitrary delay and arbitrary level of added noise. The performance of DWEA is better than those of Wiener filtered-ensemble averaging and of conventional ensemble averaging. DWEA is endurable up to added noise gain of 7 for 10 % mean square error limit. Throughout the experimentation observation, it has been demonstrated that DWEA can be applied to enhance the evoked potential having the synchronization mismatch with added noise.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.777-780
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• 2005

모바일 오디오 적용을 위한 저전력 ${\Sigma}{\Delta}$ Modulator 에 대한 설계와 layout 을 보였다. 전체 구조는 3 차 단일 피드백 루프이며, 해상도는 16bit 을 갖는다. 샘플링 주파수에 따른 Over-sampling Ratio 는 128(46kHz) 또는 64(96kHz) 가 되도록 하였다. 차동 구조를 사용한 3 차 ${\Sigma}{\Delta}$ modulator 내의 적분기에 사용된 Op-Amp 는 DC-Gain 을 높이기 위해서 Gain-boosting 기법이 적용되었다. ${\Sigma}{\Delta}$ modulator 의 기준 전압은 전류 모드 Band-Gap Reference 회로에서 공급이 되며, PVT(Process, Voltage, Temperature) 변화에 따른 기준 전압의 편차를 보정하기 위하여, binary 3bit 으로 선택하도록 하였다. DAC 에서 사용되는 단위 커패시터의 mismatch 에 의한 성능 감소를 막기 위해, DAC 신호의 경로를 임의적으로 바꿔주는 scrambler 회로를 이용하였다. 4bit Quantizer 내부의 비교기 회로는 고해상도를 갖도록 설계하였고, 16bit thermometer code 에서 4bit binary code 변환시 발생하는 에러를 줄이기 위해 thermometer-to-gray, gray-to-binary 인코딩 방법을 적용하였다. 0.18um CMOS standard logic 공정 내 thick oxide transistor(3.3V supply) 공정을 이용하였다. 입력 전압 범위는 2.2Vp-p,diff. 이며, Typical process, 3.3V supply, 50' C 시뮬레이션 조건에서 2Vpp,diff. 20kHz sine wave 를 입력으로 할 때 SNR 110dB, THD 는 -95dB 이상의 성능을 보였고, 전류 소모는 6.67mA 이다. 또한 전체 layout 크기는 가로 1100um, 세로 840um 이다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

• Asian-Australasian Journal of Animal Sciences
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• v.27 no.3
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• pp.316-323
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• 2014

We previously identified quantitative trait loci (QTL) for body weight and average daily gain in a common region between ADL0198 (chr 1: 171.7 Mb) and ABR0287 (chr 1: 173.4 Mb) on chicken chromosome 1 in an $F_2$ resource population produced by crossing low- and high-growth lines of the Hinai-dori breed. Motilin receptor (MLNR) is a candidate gene affecting growth traits in the region. In this study, we genotyped polymorphisms of the MLNR gene and investigated its association with growth traits in a Hinai-dori $F_2$ intercross population. All the exons of the MLNR gene in the parental population were subjected to PCR amplification, nucleotide sequenced and haplotypes identified. To distinguish resultant diplotype individuals in the $F_2$ population, a mismatch amplification mutation assay was performed. Three haplotypes (Haplotypes 1-3) were accordingly identified. Six genotypes produced by the combination of three haplotypes (Haplotype 1, 2, and 3) were examined in order to identify associations between MLNR haplotypes and growth traits. The data showed that Haplotype 1 was superior to Haplotype 2 and 3 in body weight at 10 and 14 weeks of age, average daily gain between 4 and 10 weeks, 10 and 14 weeks, and 0 and 14 weeks of age in female in $F_2$ females. It was concluded that MLNR is a useful marker of growth traits and could be used to develop strategies for improving growth traits in the Hinai-dori breed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11A
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• pp.1812-1819
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• 2001

In this paper, it investigated the permitted limit of the analog nonideality for the SOSOC Σ-Δ modulator design which is satisfied with 1 [MHz] signal bandwidth and 12-bit resolution in the OSR=25. Firstly, it get the SOSOC Σ-Δ modulator model and gain coefficient which is suitable in low voltage for the Σ-Δ modulator design which is satisfied with the specification in the supply voltage 3.3 [Vl. And it provided the performance prediction of the Σ-Δ modulator and the permitted limit of the nonideality by adding the performance degradation facts of the Σ-Δ modulator such as the finite gain of the amplifier, the SR, the closed-loop pole, the switch ON resistance and the capacitor mismatch to the ideal Σ-Δ modulator model. When designed the Σ-Δ modulator which is satisfied with the specification by the base above, it will be able to predict the performance of the Σ-Δ modulator and the guide for the specification of the circuit which composes the Σ-Δ modulator.