• Title/Summary/Keyword: fuse

Search Result 534, Processing Time 0.023 seconds

A Study of Re-Fuse Coordination Method of Distribution System with SFCL (배전계통에 초전도 전류제한기 적용 시 Relcoser-Fuse 협조 방법에 관한 연구)

  • Kim, Myoung-Hoo;Kim, Jin-Seok;You, Il-Kyoung;Moon, Jong-Fil;Lim, Sung-Hun;Kim, Jae-Chul
    • The Transactions of The Korean Institute of Electrical Engineers
    • /
    • v.58 no.10
    • /
    • pp.1835-1841
    • /
    • 2009
  • We analyze the problem of recloser-fuse coordination when a superconducting fault current limiter (SFCL) is installed to a power distribution system. Generally, The recloser is installed to upstream of fuse to protect against both permanent fault and temporary one appropriately. However, in a power distribution system with SFCL, the fault current is decreased by the effect of the impedance value of the SFCL and when a permanent fault occurs, the fuse may not melt during the last delay operation of the recloser because of the insufficient heat from the decreased current. Therefore, when SFCLs are applied into a power distribution system, the rating of the fuse has to be reselected to coordinate recloser to fuse effectively. To solve these problems, this paper analysed the operation of recloser-fuse coordination and presented the improved recloser-fuse coordination method in a power distribution system with SFCL using PSCAD/EMTDC.

Design of an eFuse OTP Memory of 8 Bits for PMICs and its Measurement (PMIC용 8비트 eFuse OTP Memory 설계 및 측정)

  • Park, Young-Bae;Choi, In-Hwa;Lee, Dong-Hoon;Jin, Liyan;Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2012.05a
    • /
    • pp.722-725
    • /
    • 2012
  • In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory based on a $0.35{\mu}m$ BCD process using differential paired eFuse cells which can sense BL data without a reference voltage and also have smaller sensing resistances of programmed eFuse links. The channel widths of a program transistor of the differential eFuse OTP cell are splitted into $45{\mu}m$ and $120{\mu}m$. Also, we implement a sensing margin test circuit with variable pull-up loads in consideration of variations of the programmed eFuse resistances. It is confirmed by measurement results that the designed 8-bit eFuse OTP memory IP gives a better yield when the channel width is $120{\mu}m$.

  • PDF

Design for a Fuse Element of Sub-miniature Fuse with High Breaking Capacity Characteristics (높은 차단용량 특성을 갖는 초소형 미니어처 퓨즈의 가용체 설계)

  • Ahn, Chang Hwan
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.54 no.3
    • /
    • pp.131-137
    • /
    • 2017
  • In order to safely protect high over current flowing into the main circuit at short-circuit without any explosion or fire, the enclosed cartridge fuse with a high interrupting capacity should be applied. But this fuse is impossible to be applied to an inner electronic circuit because of a limited space problem result from the miniaturization trend of products. Therefore, it is necessary to apply a sub-miniature fuse with a relatively small size. However the semi-enclosed fuse which is more free for an influx of air than the enclosed cartridge fuse and is possible to protect fuse elements with chemical and physical combination can be adoptable. But it has a limit of implementing the characteristic of a high breaking capacity. For these reasons, the Fe-42wt%Ni fuse elements alloy and fuse-link with less space were designed to increase a breaking capacity of sub-miniature fuse and its safety for fire and explosion was confirmed in this paper.

Design of PMOS-Diode Type eFuse OTP Memory IP (PMOS-다이오드 형태의 eFuse OTP IP 설계)

  • Kim, Young-Hee;Jin, Hongzhou;Ha, Yoon-Gyu;Ha, Pan-Bong
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
    • /
    • v.13 no.1
    • /
    • pp.64-71
    • /
    • 2020
  • eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

고압 Fuse의 차단시험

  • 신대승
    • 전기의세계
    • /
    • v.31 no.9
    • /
    • pp.613-624
    • /
    • 1982
  • 본고의 내용은 다음과 같다. 1. 고압 Fuse의 종류 2. 고압 Fuse의 차단현상 3. 고압 Fuse의 차단시험

  • PDF

Design of High-Reliability Differential Paired eFuse OTP Memory for Power ICs (Power IC용 고신뢰성 Differential Paired eFuse OTP 메모리 설계)

  • Park, Young-Bae;Jin, Li-Yan;Choi, In-Hwa;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.17 no.2
    • /
    • pp.405-413
    • /
    • 2013
  • In this paper, a high-reliability differential paired 24-bit eFuse OTP memory with program-verify-read mode for PMICs is designed. In the proposed program-verify-read mode, the eFuse OTP memory can do a sensing margin test with a variable pull-up load in consideration of programmed eFuse resistance variation and can output a comparison result through a PFb (pass fail bar) pin by comparing a programmed datum with its read one. It is verified by simulation results that the sensing resistance is lower with $4k{\Omega}$ in case of the designed differential paired eFuse OTP memory than $50k{\Omega}$ in case of its dual-port eFuse OTP memory.

Design of a 32-Bit eFuse OTP Memory for PMICs (PMIC용 32bit eFuse OTP 설계)

  • Kim, Min-Sung;Yoon, Keon-Soo;Jang, Ji-Hye;Jin, Liyan;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.15 no.10
    • /
    • pp.2209-2216
    • /
    • 2011
  • In this paper, we design a 32-bit eFuse OTP memory for PMICs using MagnaChip's $0.18{\mu}m$ process. We solve a problem of an electrical shortage between an eFuse link and the VSS of a p-substrate in programming by placing an n-well under the eFuse link. Also, we propose a WL driver circuit which activates the RWL (read word-line) or WWL (write word-line) of a dual-port eFuse OTP memory cell selectively when a decoded WERP (WL enable for read or program) signal is inputted to the eFuse OTP memory directly. Furthermore, we reduce the layout area of the control circuit by removing a delay chain in the BL precharging circuit. We'can obtain an yield of 100% at a program voltage of 5.5V on 94 manufactured sample dies when measured with memory tester equipment.

A Study on the Causal Analysis of Electrical Fire by Using Fuse (퓨즈를 이용한 전기화재의 원인분석에 관한 연구)

  • Lee, Chun-Ha;Kim, Shi-Kuk;Ok, Kyung-Jae
    • Fire Science and Engineering
    • /
    • v.22 no.1
    • /
    • pp.24-28
    • /
    • 2008
  • This paper studied on the causal analysis of electrical fire by using fuse that it is used with safety device in electrical products. The experimental samples used are glass tube fuse(15 A, $5{\times}20mm$) and temperature fuse(10 A, $72^{\circ}C$). The experiment analyzed on the characteristics of damaged fuse by main causes(short circuit, overload, external flame) of electrical fire. The results showed, in case of glass tube fuse identified different characteristics in external form and element surface and element texture of damaged fuse by main causes of electrical fire. In case of temperature fuse identified different characteristics in external form and sliding contact surface and sliding contact texture of damaged fuse only by external flame.

Empirical Modeling on the Breaking Characteristics of Power Current Limited Fuse (전력용 백업퓨우즈 차단특성 모델링)

  • Lee Sei-Hyun;Lee Bvung-Sung;Han Sang-Ok
    • The Transactions of the Korean Institute of Electrical Engineers C
    • /
    • v.54 no.9
    • /
    • pp.391-396
    • /
    • 2005
  • In this paper the modeling of interrupting characteristics of a high voltage current limiting fuse to be used in a power distribution system is introduced. In order to reduce the level of energy which can be absorbed by equipment during fault current flow, a high voltage current limiting fuse can generate a high voltage at the fuse terminals. Consequently it is necessary to model and analyze precisely the voltage and current variation during a CL fuse action. The characteristics of CL fuse operation modeled by electrical components have been performed with less than 6 [$\%$] errors. So the fuse designer or manufacturer can estimate the characteristics of CL fuse operation by using this modeling. The Electro Magnetic Transient Program (EMTP) is used to develop the modeling.

Assessment for Failure Probability of Landing Gear Structural Fuse and Improvement Measure (착륙장치용 Structural Fuse 파손확률 계산 및 개선 방안)

  • Lee, Seung-Gyu;Kim, Tae-Uk;Hwang, In-Hee;Lee, Jeong-Sun;Jo, Jeong-Jun;Park, Chong-Yeong
    • Proceedings of the KSME Conference
    • /
    • 2008.11a
    • /
    • pp.469-474
    • /
    • 2008
  • The reason for crashworthy landing gear is to contribute to the overall aircraft design goals in the event of a crash. One of crashworthy landing gear design approaches is inclusion of structural fuse. Structural fuse is used to control the mode of failure of landing gear. If structural fuse doesn't work at desired condition, other unexpected accidents can occur. In this paper, failure probability is calculated for landing gear structural fuse and improvement measure is introduced to improve failure probability of structural fuse.

  • PDF