• Steel and Composite Structures
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• v.47 no.3
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• pp.315-337
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• 2023

The steel structure is an assembly of individual structural members joined together by connections. The connections are the focal point to transfer the forces which is susceptible to damage easily. It is challenging to replace the affected connection parts after an earthquake. Hence, steel plates are utilised as a structural fuse that absorbs connection forces and fails first. The objective of the present research is to develop a beam-column end plate connection with single and dual fuse and study the effect of single fuse, dual fuse and combined action of fuse and damper. In this research, seismic resilient beam-column end plate connection is developed in the form of structural fuse. The novel connection consists of one main fuse was placed horizontally and secondary fuse was placed vertically over main fuse. The specimens are fabricated with the variation in number of fuse (single and dual) and position of fuse (beam flange top and bottom). From the fabricated ten specimens five specimens were loaded monotonically and five cyclically. The experimental results are compared with Finite Element Analysis results of Arunkumar and Umamaheswari (2022). The results are critically assessed in the aspect of moment-rotation behaviour, strain in connection components, connection stiffness, energy dissipation characteristics and ductility. While comparing the performance of total five specimens, the connection with fuse exhibited superior performance than the conventional connection. An equation is proposed for the moment of resistance of end-plate connection without and with structural fuse.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.21-30
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• 2012

Technology trend and application of laser fuse, anti-fuse, and eFUSE as well as the structure, programming mechanism, and reliability of eFUSE have been reviewed. In order to ensure eFUSE reliability in the field, a sensing circuit trip point consistent with the fuse resistance distribution, process variation, and device degradation in the circuit such as hot carrier or NBTI, as well as fuse resistance reliability must be considered to optimize and define a reliable fuse programming window.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.317-326
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• 2016

In this paper, a logic eFuse (electrical Fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) using only logic transistors to reduce the development cost and period of OTP memory IPs is designed. To secure the reliability of other IPs than the OTP memory IP, a higher voltage of 2,4V than VDD (=1.5V) is supplied to only eFuse links of eFuse OTP memory cells directly through an external pad FSOURCE coming from test equipment in testing wafers. Also, an eFuse OTP memory cell of which power is supplied through FSOURCE and hence the program power is increased in a two-dimensional memory array of 128 rows by 8 columns being also able to make the decoding logic implemented in small area. The layout size of the designed 1kb eFuse OTP memory IP with the Dongbu HiTek's 110nm CIS process is $295.595{\mu}m{\times}455.873{\mu}m$ ($=0.134mm^2$).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.687-691
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• 2011

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory in consideration of EM (electro-migration) and eFuse resistance variation based on a $0.18{\mu}m$ generic process, which is used for an analog trimming application. First, we use an external program voltage to increase the program power applied an eFuse. Secondly, we apply a scheme of precharging BL to VSS prior to RWL (read word line) activation and optimize read NMOS transistors to reduce the read current flowing through a non-programmed cell. Thirdly, we design a sensing margin test circuit with a variable pull-up load out of consideration for the eFuse resistance variation of a programmed eFuse. Finally, we increase program yield of eFuse OTP memory by splitting the length of an eFuse link.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.741-743
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• 2008

본 논문에서는 초고압 송전선의 조상설비나 안전도가 요구되는 변전설비 등에서 역률 개선용으로 사용되는 전력용 콘덴서의 Fuse를 설계하기 위해 Fuse 용단시험을 통해서 구한 Fuse 설계 데이터를 제시하고자 한다. 그리고, 제시한 데이터를 이용하여 주어진 사양의 전력용 콘덴서에 대하여 요구되는 실제 Fuse를 선정하여 적용하고 시제품을 제작하여 Fuse 동작시험을 실시한 결과를 제시하고자 한다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.168-175
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• 2017

In this paper, a 5V small-area NMOS-diode eFuse OTP memory cell is proposed. This cell which is used in PMICs consists of a 5V NMOS transistor and an eFuse link as a memory part, based on a BCD process. Also, a regulated voltage of V2V ($=2.0V{\pm}10%$) instead of the conventional VDD is used to the pull-up loads of a VREF circuit and a BL S/A circuit to obtain a wider operational voltage range of the eFuse memory cell. When this proposed cells are used in the simulation, their sensing resistances are found to be $15.9k{\Omega}$ and $32.9k{\Omega}$, in the normal read mode and in the program-verify-read mode, respectively. Furthermore, the read current flowing through a non-blown eFuse is restricted to $97.7{\mu}A$. Thus, the eFuse link of a non-blown eFuse OTP memory cell is kept non-blown. The layout area of the designed 1kb eFuse OTP memory IP based on Dongbu HiTek's BCD process is $168.39{\mu}m{\times}479.45{\mu}m(=0.08mm^2)$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.509-518
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• 2023

In this paper, we designed a 4Kb poly-fuse OTP IP (Intellectual Property) required for analog circuit trimming and calibration. In order to reduce the BL resistance of the poly-fuse OTP cell, which consists of an NMOS select transistor and a poly-fuse link, the BL stacked metal 2 and metal 3. In order to reduce BL routing resistance, the 4Kb cells are divided into two sub-block cell arrays of 64 rows × 32 rows, with the BL drive circuit located between the two 2Kb sub-block cell arrays, which are split into top and bottom. On the other hand, in this paper, we propose a core circuit for an OTP cell that uses one poly-fuse link to one select transistor. In addition, in the early stages of OTP IP development, we proposed a data sensing circuit that considers the case where the resistance of the unprogrammed poly-fuse can be up to 5kΩ. It also reduces the current flowing through an unprogrammed poly-fuse link in read mode to 138㎂ or less. The poly-fuse OTP cell size designed with DB HiTek 90nm CMOS process is 11.43㎛ × 2.88㎛ (=32.9184㎛2), and the 4Kb poly-fuse OTP IP size is 432.442㎛ × 524.6㎛ (=0.227mm²).

• 전자공학회논문지 IE
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• v.47 no.4
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• pp.28-33
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• 2010

In this paper, we proposed to the inspection algorithm for cap, Electric fuse is an over current and circuit protection device which is occurred in electric & electronic appliance. Also the fuse are protection the second hazard at arc etc. Fuse are interest regarding a safety increased. Consequently, the fuse came to be very important. Cap inspection algorithm is designed for the cap of fuse. CCD camera is monitering the solder of cap distribution map. The conditioning of fuse cap; suming all searching data with non solder area. the area is bigger reference data then the cap is bad cap.

• Aerospace Engineering and Technology
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• v.11 no.1
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• pp.1-6
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• 2012

Power system in satellite is protected by installing fuses, LCLs (Latching Current Limiters), etc. between satellite power supply and loads. In this paper, the fuse sizing technique for satellite power system protection is addressed. Detailed fuse sizing method is explained and it is shown that the single fuse connection method is mathematically subordinated to the parallel fuse connection method. In addition, appropriate fuse selection method is newly suggested under a situation where exact current characteristics of a load connected to a fuse is unknown.

• Journal of the Korean Society of Safety
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• v.28 no.5
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• pp.15-20
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• 2013

This paper dealt with melting characteristics of low-voltage miniature cartridge fuse used for 220 V electronic equipment. The experimental sample is low-voltage miniature cartridge fuse with rating of 250 V(3A) and size of $5{\times}20$ mm. In order to evaluate melting and scattering characteristics of the fuse, we applied to 8/20 ${\mu}s$ surge current, overload current and external thermal stress such as flame of fire. From the experimental results, the fuse element was melted and scattered by applied surge current(above 0.79 kA) and overload current(above 4.5 A). It was also attached to the inner surface of the fuse tube. The fuse element was attached as a thin film on inner surface of fuse tube when large surge current was applied. It was confirmed, however, the fuse element was not changed by external thermal stress such as flame and hot-air.