• 제목/요약/키워드: functional gate

검색결과 118건 처리시간 0.021초

자동 분수공의 개발 (Development of the Automatic Turnout)

  • 저하우;이남호;김성준;최진용;한형근;한휘남
    • 한국농공학회지
    • /
    • 제36권4호
    • /
    • pp.33-38
    • /
    • 1994
  • Floating-type automatic turnout was developed for the purpose of reducing labor cost and labor-working hours related to turnout management. The point of automation is to use a flexible-float within the turnout. The weight of float is changed by emptying and filling with water at the beginning and ending of irrigation. The turnout is controlled to open and close small bole on the float bottom using electromagnets. With the weight control of float. the gate of turnout is opened by the empty float to begin irrigatiom and is closed by the filled float to stop irrigation. The turnout was designed to be operated by the main computer and to minimize electric power consumption by sending an electric current at the beginning and ending of irrigation. The functional experiment was succesfully carried out and the rating curves for both free overflow condition and submerged flow condition were derived.

  • PDF

조선 후기 영건의궤에 실린 안초공의 기능과 표기법 연구 (A Study on Functions and Transcriptions of Anchogongs in Yeonggeonuigwes of Late Joseon Period)

  • 이우종
    • 건축역사연구
    • /
    • 제27권4호
    • /
    • pp.7-16
    • /
    • 2018
  • This study is focusing on anchogongs(按草工) in yeonggeonuigwes(營建儀軌), which were recorded with few details and in unsettled transcriptions. First, the positions and functions of anchogongs in $18^{th}$ censtury are analyzed by comparing to anchogongs in more detailed early $19^{th}$ century yeonggeonuigwes and those in extant buildings. Second, with the result, the historical significances are presumed in changing transcriptions of anchogong terms in those uigwes. In $18^{th}$ century uigwes, most of anchogongs are functioned as matbo-anchogongs and only four anchogongs in a gate building were used as jongryang-anchogongs. It is mainly because the sorts of buildings in $18^{th}$ century yeonggeonuigwes had only several varieties: most of the buildings belonging royal shrines. Transcriptions of anchogong terms had been changed for reflecting functional developments of anchogongs in $18^{th}$ century. However, reflections were much later than changes of actual functions.

IDDQ 테스트 방식을 이용한 CMOS 논리회로의 고장분석에 관한 연구 (A study on the fault analysis of CMOS logic circuit using IDDQ testing technique)

  • Han, Seok-Bung
    • 전자공학회논문지B
    • /
    • 제31B권9호
    • /
    • pp.1-9
    • /
    • 1994
  • This paper analyzes the faults and their mechanism of CMOS ICs using IDDQ testing technique and evalutes the reliability of the chips that fail this test. It is implemented by the three testing phases, initial test, burn-in and life test. Each testing phase includes the parametric test, functional test, IDDQ test and propagation delay test. It is shown that the short faults such as gate-oxide short, bridging can be only detected by IDDQ testing technique and the number of test patterns for this test technique is very few. After first burn-in, the IDDQ of some test chips is decreased, which is increased in conventional studies and in subsequent burn-in, the IDDQ of all test chips is stabilized. It is verified that the resistive short faults exist in the test chips and it is deteriorated with time and causes the logic fault. Also, the new testing technique which can easily detect the rsistive short fault is proposed.

  • PDF

Testbench Implementation for FPGA based Nuclear Safety Class System using OVM

  • Heo, Hyung-Suk;Oh, Seungrohk;Kim, Kyuchull
    • 전기전자학회논문지
    • /
    • 제18권4호
    • /
    • pp.566-571
    • /
    • 2014
  • A safety class field programmable gate array based system in nuclear power plant has been developed to improve the diversity. Testbench is necessary to satisfy the technical reference, IEC-62566, for verification and validation of register transfer level code. We use the open verification methodology(OVM) developed by standard body. We show that our testbench can use random input for test. And also we show that reusability of block level testbench for the integration level testbench, which is very efficient for large scale system like nuclear reactor protection system.

기능성 원자간력 현미경 캔틸레버 제조 방법과 특성 (Method of manufacturing and characteristics of a functional AFM cantilever)

  • 서문식;이철승;이경일;신진국
    • 정보저장시스템학회:학술대회논문집
    • /
    • 정보저장시스템학회 2005년도 추계학술대회 논문집
    • /
    • pp.56-58
    • /
    • 2005
  • To illustrate an application of the field effect transistor (FET) structure, this study suggests a new cantilever, using atomic force microscopy (AFM), for sensing surface potentials in nanoscale. A combination of the micro-electromechanical system technique for surface and bulk and the complementary metal oxide semiconductor process has been employed to fabricate the cantilever with a silicon-on-insulator (SOI) wafer. After the implantation of a high-ion dose, thermal annealing was used to control the channel length between the source and the drain. The basic principle of this cantilever is similar to the FET without a gate electrode.

  • PDF

AC-3와 MPEG-2 오디오 공용 복호화기의 설계 (A design of dual AC-3 and MPEG-2 audio decoder)

  • 고우석;유선국;박성욱;정남훈;김준석;이근섭;윤대희
    • 한국통신학회논문지
    • /
    • 제23권6호
    • /
    • pp.1433-1442
    • /
    • 1998
  • The thesis presents a dual audio decoder which can decode both AC-3 and MPEG-2 bitstream. The MPEG-2 synthesis processi s optimized via FFT to establish the common data path with AC-'3s. A dual audio decoder consists of a DSP core which performs the control-intensive part of each algorithm and a common synthesis filter which perfomrs the computation-intensive part. All the components of the dual audio decoder have been described in VHDL and simulated with a SYNOPSYS tool. The software modeling of the DSP core was used for functional validation. After being synthesized using 0.6 .mu.m-3ML technology standard cell, the dual audio decoder was simulated at gate-level with a COMPASS tool for hardware validation.

  • PDF

근 반응제거를 위한 적응필터 설계와 FPGA 구현 (Design of Adaptive Filter for Muscle Response Suppression and FPGA Implementation)

  • 염호준;박영철;윤형로
    • 대한전기학회논문지:시스템및제어부문D
    • /
    • 제52권12호
    • /
    • pp.708-716
    • /
    • 2003
  • The surface EMG signal detected from voluntarily activated muscles can be used as a control signal for functional electrical stimulation. To use the voluntary EMG signal, it is necessary to eliminate the muscle response evoked by the electrical stimulation and enable to process the algorithm in real time. In this paper, we propose the Gram-Schmidt(GS) algorithm and implement it in FPGA(field programmable gate array). GS algorithm is efficient to eliminate periodic signals like muscle response, and is more stable and suitable to FPGA implementations than the conventional least-square approach, due to the systolic array structure.

VLSI 지향적인 APP용 2-D SYSTOLIC ARRAY PROCESSOR 설계에 관한 연구 (A Study on VLSI-Oriented 2-D Systolic Array Processor Design for APP (Algebraic Path Problem))

  • 이현수;방정희
    • 전자공학회논문지B
    • /
    • 제30B권7호
    • /
    • pp.1-13
    • /
    • 1993
  • In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

  • PDF

인천항 기능 재배치에 따른 갑문의 대기 시뮬레이션 연구 (A Study on the Queueing Simulation of Lock Gates according to the Functional Rearrangement in Incheon Port)

  • 구자윤
    • 한국항해항만학회지
    • /
    • 제31권3호
    • /
    • pp.205-212
    • /
    • 2007
  • 인천항에서는 인천대교 건설을 계기로 남외항 건설을 추진함과 더불어 인천 내항 등의 기능 재배치가 추진되고 있다. 본 논문은 기능 재배치 계획에 따라 2011년과 2015년의 해상교통량을 추정하고, 내항의 갑문 운용에 따른 선박의 대기시간을 항만운용 시뮬레이션에 의하여 분석하여 내항에 기항하는 선박들의 체선 체화비용을 산정 분석하고자 하였으며, 최종적으로 2011년부터 2015년까지 내항에 기항하던 컨테이너선들의 남항/남외항으로의 이전에 따른 경제적 효과를 평가하고자 한다. 주요한 연구결과는 다음과 같다. (1) 갑문 이용율이 약 $7\sim8%P$ 낮아졌다. (2) 갑문 대기시간 및 체선 체화비용이 약 25%P 절감되는 효과가 나타났다. (3) 자문 이용료와 선석 이전에 따른 항로 단축 편익 등을 제외하고 갑문 운용에 따라 발생되는 체선 체화비용은 연간 약 8억원의 절감효과가 있었다.

Remote O2 plasma functionalization for integration of uniform high-k dielectrics on large area synthesized few-layer MoSe2

  • Jeong, Jaehun;Choi, Yoon Ho;Park, Dambi;Cho, Leo;Lim, Dong-Hyeok;An, Youngseo;Yi, Sum-Gyun;Kim, Hyoungsub;Yoo, Kyung-Hwa;Cho, Mann?Ho
    • 한국진공학회:학술대회논문집
    • /
    • 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
    • /
    • pp.281.1-281.1
    • /
    • 2016
  • Transition metal dichalcogenides (TMDCs) are promising layered structure materials for next-generation nano electronic devices. Many investigation on the FET device using TMDCs channel material have been performed with some integrated approach. To use TMDCs for channel material of top-gate thin film transistor(TFT), the study on high-k dielectrics on TMDCs is necessary. However, uniform growth of atomic-layer-deposited high-k dielectric film on TMDCs is difficult, owing to the lack of dangling bonds and functional groups on TMDC's basal plane. We demonstrate the effect of remote oxygen plasma pretreatment of large area synthesized few-layer MoSe2 on the growth behavior of Al2O3, which were formed by atomic layer deposition (ALD) using tri-methylaluminum (TMA) metal precursors with water oxidant. We investigated uniformity of Al2O3 by Atomic force microscopy (AFM) and Scanning electron microscopy (SEM). Raman features of MoSe2 with remote plasma pretreatment time were obtained to confirm physical plasma damage. In addition, X-ray photoelectron spectroscopy (XPS) was measured to investigate the reaction between MoSe2 and oxygen atom after the remote O2 plasma pretreatment. Finally, we have uniform Al2O3 thin film on the MoSe2 by remote O2 plasma pretreatment before ALD. This study can provide interfacial engineering process to decrease the leakage current and to improve mobility of top-gate TFT much higher.

  • PDF