• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.500-500
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• 2011

With recent advances in flexible and stretchable electronics, the development of physically responsive field-effect transistors (physi-FETs) that are easily integrated with transformable substrates may enable the omnipresence of physical sensing devices in electronic gadgets. However, physical stimuli typically induce whole sensing physi-FET devices under global influences that also cause changes in the parameters of FET transducers, such as channel mobility and dielectric capacitance that prevent proper interpretations of response in sensing materials. Extended-gate structures with isolated stimuli have been used recently in physi-FETs to demonstrate performances of sensing materials only. However, such approaches are limited to prototype researches since isolated stimuli rarely occur in real-life applications. In this report, we theoretically and experimentally demonstrated that integrating piezoelectric nanocomposites directly into flexible organic FETs (OFETs) as gate dielectrics provides a general research direction to physi-FETs with a simple device structure and the capability of precisely investigating functional materials. Measurements with static stimulations, which cannot be performed in conventional systems, exhibited giant-positive d33 values of nanocomposites of barium titanate (BT) NPs and poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)).

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.21 no.6
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• pp.250-265
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• 2022

Positive effects such as significantly reducing traffic accidents caused by human error can be expected by the introduction of Automated vehicles (AV). However, as new traffic safety issues are expected to occur in the future due to errors in H/W or S/W of autonomous vehicles and lack of its function, it is necessary to establish a scenario to evaluate the driving safety of AV. Therefore, in this study, functional scenario was developed to evaluate the driving safety of AV based on traffic accident data of the National Police Agency. Using the GIS program, QGIS, traffic accident data that occurred in the toll gate and ramp sections of expressway were extracted and accident summary items were checked to classify the types of accident. In addition, based on the results of accident type classification, functional scenario were developed that contains various dangerous situations in the tollgate and ramp sections.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• Advances in nano research
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• v.15 no.3
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• pp.263-275
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• 2023

The electron transport properties of Y-type zigzag branched carbon nanotubes (CNTs) are of great significance for micro and nano carbon-based electronic devices and their interconnection. Based on the semi-empirical method combining tight-binding density functional theory and non-equilibrium Green's function, the electron transport properties between the branches of Y-type zigzag branched CNT are studied. The results show that the drain-source current of semiconducting Y-type zigzag branched CNT (8, 0)-(4, 0)-(4, 0) is cut-off and not affected by the gate voltage in a bias voltage range [-0.5 V, 0.5 V]. The current presents a nonlinear change in a bias voltage range [-1.5 V, -0.5 V] and [0.5 V, 1.5 V]. The tangent slope of the current-voltage curve can be changed by the gate voltage to realize the regulation of the current. The regulation effect under negative bias voltage is more significant. For the larger diameter semiconducting Y-type zigzag branched CNT (10, 0)-(5, 0)-(5, 0), only the value of drain-source current increases due to the larger diameter. For metallic Y-type zigzag branched CNT (12, 0)-(6, 0)-(6, 0), the drain-source current presents a linear change in a bias voltage range [-1.5 V, 1.5 V] and is symmetrical about (0, 0). The slope of current-voltage line can be changed by the gate voltage to realize the regulation of the current. For three kinds of Y-type zigzag branched CNT with different diameters and different conductivity, the current-voltage curve trend changes from decline to rise when the branch of drain-source is exchanged. The current regulation effect of semiconducting Y-type zigzag branched CNT under negative bias voltage is also more significant.

• ETRI Journal
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• v.25 no.5
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• pp.328-336
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• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.1-7
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• 2013

In this paper, a biosensor based on a gated lateral bipolar junction transistor (BJT) is proposed. The gated lateral BJT can function as both a metal-oxide-semiconductor field-effect transistor (MOSFET) and a BJT. By using the self-assembled monolayer (SAM) method, the C-reactive protein antibodies were immobilized on the floating gate of the device as the sensing membrane. Through the experiments, the characteristics of the biosensor were analyzed in this study. According to the results, it is indicated that the gated lateral BJT device can be successfully applied as a biosensor. Additionally, we found that the sensitivity of the gated lateral BJT can be varied by adjusting the emitter (source) bias.

• Journal of Information Processing Systems
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• v.15 no.2
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• pp.374-385
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• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

• Journal of the Korean Society of Combustion
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• v.21 no.4
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• pp.1-5
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• 2016

The aim of this study is to compare the effectiveness of turbo chargers on engines for off-road use when combined with WGT and VGT technologies. The effectiveness of turbo chargers was measured and performance was compared using a functional model. Exhaust characteristics were compared using WGT and VGT technologies through a gas analyzer. Results showed VGT technology was more effective at high RPM compared to WGT technology. When it came to maximising turbo performance, VGT was more effective than WGT in every test. WGT and VGT produced similar exhaust NOx levels, whereas the VGT was more effective on the PM.

• The Journal of the Acoustical Society of Korea
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• v.18 no.1
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• pp.92-96
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• 1999

As CMOS technologies have been rapidly developed, bridging faults have been relatively increased. IDDQ testing is a current testing methodology which can enhance reliability of the circuit since it efficiently detects bridging faults that are difficult to detect by functional testing. In this paper we consider internal bridging faults occurred in each gate of logic circuits under test and finally develop a fault simulator for IDDQ testing to detect assumed bridging faults.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.11-14
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• 2007

CMOS technology 기반의 고주파 직접회로에서는 충분한 이득과 안정성을 얻기 위하여 inductor, capacitor와 같은 수동 소자를 적절히 사용하여 설계하여야 한다. 이와 같은 수동 소자는 CMOS 집적회로에서 넓은 면적을 차지하는 단점이 있다. 고주파 증폭기의 부하를 능동 소자로 대체하게 되면 작은 크기로 회로의 제작이 가능하게 되나, 능동 소자는 수동 소자에 비하여 선형 특성이 좋지 않기 때문에 실제로 고주파 증폭기 설계에 사용하지 않는다. 본 논문에서는 이와 같은 능동 소자의 비선형성을 억제하면서, 동시에 회로의 크기를 줄일 수 있는 기능성 능동 부하를 적용한 고주파 증폭기를 설계하였다. 기능성 능동 부하는 2개의 MOSFET은 대칭으로 연결된 구조를 가지며, 하나의 MOSFET은 일반적인 load로 동작하며, 다른 MOSFET은 gate에 가변 전압을 인가함으로써, 증폭기의 전달함수를 변화시킬 수 있다. 이와 같은 특성을 이용하여 고주파 증폭기의 선형성을 보상할 수가 있다.