• ETRI Journal
• /
• 제36권6호
• /
• pp.942-952
• /
• 2014

This paper presents a novel test point insertion (TPI) method for a pseudo-random built-in self-test (BIST) to reduce the area overhead. Recently, a new TPI method for BISTs was proposed that tries to use functional flip-flops to drive control test points instead of adding extra dedicated flip-flops for driving control points. The replacement rule used in a previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip-flops. This paper proposes a logic cone analysis-based TPI approach to overcome the limitations. Logic cone analysis is performed to find candidate functional flop-flops for replacing dedicated flip-flops. Experimental results indicate that the proposed method reduces the test point area overhead significantly with minimal loss of testability by replacing the dedicated flip-flops.

• 대한전기학회논문지:전력기술부문A
• /
• 제48권9호
• /
• pp.1161-1166
• /
• 1999

Delay testing has become highlighted in the field of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new scan filp-flop is devised which can be used for both stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied to both the existing functional justification method and the newly-developed reverse functional justification method which uses scan flip-flops as storing the second test patterns rather than the first test patterns. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased by about 10% on the average.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제6권3호
• /
• pp.154-161
• /
• 2006

This paper describes the new types of ngative differential resistance (NDR) IC applications which use a monolithic quantum-effect device technology based on the RTD/HBT heterostructure design. As a digital IC, a low-power/high-speed MOBILE (MOnostable-BIstable transition Logic Element)-based D-flip flop IC operating in a non-return-to-zero (NRZ) mode is proposed and developed. The fabricated NRZ MOBILE D-flip flop shows high speed operation up to 34 Gb/s which is the highest speed to our knowledge as a MOBILE NRZ D-flip flop, implemented by the RTD/HBT technology. As an analog IC, a 14.75 GHz RTD/HBT differential-mode voltage-controlled oscillator (VCO) with extremely low power consumption and good phase noise characteristics is designed and fabricated. The VCO shows the low dc power consumption of 0.62 mW and good F.O.M of -185 dBc/Hz. Moreover, a high-speed CML-type multi-functional logic, which operates different logic function such as inverter, NAND, NOR, AND and OR in a circuit, is proposed and designed. The operation of the proposed CML-type multi-functional logic gate is simulated up to 30 Gb/s. These results indicate the potential of the RTD based ICs for high speed digital/analog applications.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
• /
• pp.1467-1470
• /
• 1987

This paper proposes a functional simulation algorithm which decrease the internal memory space and run time in simulation of VLSI. Flip-flop, register, ram, rom, ic and fun are described as functional elements in the simulator. Especially icf is made as new functional element by combining the gate and the functional element, therefore icf is used efficiently in simulation of VLSI. The proposed algorithm is implemented on PC-AT(MS-DOS) in by Prolog-1.

• ETRI Journal
• /
• 제25권3호
• /
• pp.187-194
• /
• 2003

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45 % over the conventional functional justification.

• 대한전자공학회논문지
• /
• 제13권3호
• /
• pp.1-6
• /
• 1976

이 논문에서는 Boolean difference를 이용하여 combinational 및 sequential 논리회로에서 발생하는 기능적인 고장에 대한 test pattern을 얻는 방법을 연구하였다. 이 방법은 test pattern을 얻고자 하는 회로의 Boolean 함수의 Boolean difference를 계산하므로써 체계적으로 test pattern을 얻는 절차를 보여주고 있다. 컴퓨터에 의한 실험결과에 의하며 이 방법은 combinational 회로 및 asynchronous sequential 회로에 적합하며, clock이 있는 flip flop을 적당히 모형화함으로서 이 방법을 synchronous sequential회로에도 적용할 수 있음이 입증되었다. In this paper, a method of test pattern generation for the functional failure in both combinational and sequentlal logic networks by using exterded Boole an difference is proposed. The proposed technique provides a systematic approach for the test pattern generation procedure by computing Boolean difference of the Boolean function that represents the Logic network for which the test patterns are to be generated. The computer experimental results show that the proposed method is suitable for both combinational and asynchronous sequential logic networks. Suitable models of clocked flip flops may make it possible for one to extend this method to synchronous sequential logic networks.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.433-434
• /
• 2008

In this paper, we present an improved design of the conventional ARM7 processor. It is based on the flip-flop to improve the pipeline performance of the processor. Also for improving the performance, the optimization of functional blocks and a multiplier is carried out. According to the experimental results, the maximum delay-time of functional blocks and the execution cycle of a multiplier is reduced by 33% and 2 cycles compared with a conventional design, respectively. Therefore, it leads to improve an operation speed about 30%.

• 한국정보처리학회논문지
• /
• 제2권3호
• /
• pp.425-432
• /
• 1995

본 논문에서는 VLSI 회로망의 데스트 패턴 생성에 적합한 범용 자동 데스트 패턴 생성기(UATPG)의 설계 및 구현 기법을 기술하고자 한다. UATPG는 기존 ATPG의 용량을 확장하고 CAD 사용자에게 편리한 설계 환경을 제공하는데 초점을 맞추어 구현되었다. 테스트 패턴 생성시에 함수적 게이트의 신호선 논리값확인 및 고장효과전달을 효과적 으로 수행하기 위하여 경험적인 기법을 고안하여 적용하였다. 또한, 테스트 용이화 설계(design for testability)에 사용되는 기억소자(flip-flop)가 의사 입출력으로 이 용되어 VLSI 회로망의 시험성을 한층 높여 주었다. 그 결과, UATPG는 사용의 용이성과 성능면에서 좋은 성과를 보여주었다.

• 정보처리학회논문지A
• /
• 제14A권5호
• /
• pp.301-308
• /
• 2007

본 논문에서는 위상기반 양안스테레오정합 알고리즘을 이용, 실시간으로 dense disparity map을 추출 가능한 고성능 가속기 구조를 설계하였다. 채택된 알고리즘은 웨이블릿 기반의 위상차 기법의 강건성과 위상상관 기법의 기본적인 control 기법을 결합한 Local Weighted Phase Correlation(LWPC) 스테레오정합 알고리즘으로서 4개의 주요 단계로 구성이 되어 있다. 해당 알고리즘의 효율적인 병렬 하드웨어의 설계를 위하여, 제안된 가속기는 각 단계의 기능블록은 SIMD(Single Instruction Multiple Data Stream) 모드로 동작하게 되며, 전체적으로 각 기능 블록은 파이프라인(pipeline) 모드로 실행된다. 그 결과 제안된 구조에서 제시된 파이프라인 동작 모드의 선형 배열 프로세서는 행렬 순차수행 방법에 의한 2차원 영상처리에서 전치메모리의 필요를 제거하면서도 연산의 일반성과 고효율을 유지하게 한다. 제안된 하드웨어 구조는 Xilinx HDL을 이용하여 필요한 하드웨어 자원을 look up table, flip flop, slice, memory의 소모량으로 표현하였으며, 그 결과 실시간 처리 성능의 단일 칩 구현 가능성을 보여주었다.