• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.5
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• pp.77-86
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• 1995

In this paper in order to reduce the encoding complexity required in the full search vector quantization(VQ), a new classified vector quantization(CVQ) technique is described employing the minimum-distance classifier. The determination of the optimal subcodebook sizes for each class is an important task in CVQ designs and is not an easy work. Therefore letting the subcodebook sizes be equal. A CVQ technique. Which satisties the optimal CVQ condition approximately, is proposed. The proposed CVQ is a kind of the partial search VQ because it requires a search process within each subcodebook only, and the minimum encoding complexity since the subcodebook sizes are the same in each class. But simulation results reveal while the encoding complexity is only O(N$^{1/2}$) comparing with O(N) of the full-search VQ. A simple systolic array, which has the through-put of k, is also proposed for the implementation of the VQ. Since the operation of the classifier is identical with that of the VQ, the proposed array is applied to both the classifier and the VQ in the proposed CVQ, which shows the usefulness of the proposed CVQ.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.101-112
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• 2004

In this paper, we developed a numerical analysis model by using ADI-FDTD method to analyze three-dimensional interconnect structure. We discretized maxwell's curl equation by using ADI-FDTD. Using ADI-FDTD method, a sampler circuit designed from 3.3 V CMOS technology is simplified to 3-metal line structure. Using this simplified structure, the time delay and signal distortion of complex interconnects are investigated. As results of simulation, 5∼10 ps of delay time and 0.1∼0.2 V of signal distortion are measured. As demonstrated in this paper, the full-wave analysis using ADI-FDTD exhibits a promise for accurate modeling of electromagnetic phenomena in high-speed VLSI interconnect.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.5
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• pp.34-42
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• 2002

In this paper, we designed the VLSI array architecture for the high speed processing of the motion estimation used by block matching algorithm. We derived the one dimensional systolic array from the full search block matching algorithm. The data and control signals of the proposed systolic array are passed through adjacent processing element. So proposed architecture has temporal and spatial locality. The I/O ports exists only in the first and last processing elements of the array. This architecture has low pin counts and modular expandability. So the proposed array architecture can be cascaded for different block size and search range.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.160-165
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• 2009

A 12b 2 MS/s cyclic ADC processing 3.3 Vpp single-ended rail-to-rail input signals is presented. The proposed ADC demonstrates an offset voltage less than 1 mV without well-known calibration and trimming techniques although power supplies are directly employed as voltage references. The SHA-free input sampling scheme and the two-stage switched op-amp discussed in this work reduce power dissipation, while the comparators based on capacitor-divided voltage references show a matched full-scale performance between two flash sub ADCs. The prototype ADC in a $0.18{\mu}m$ 1P6M CMOS demonstrates the effective number of bits of 11.48 for a 100 kHz full-scale input at 2 MS/s. The ADC with an active die area of $0.12\;mm^2$ consumes 3.6 m W at 2 MS/s and 3.3 V (analog)/1.8 V (digital).

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.

• Journal of Korea Multimedia Society
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• v.3 no.4
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• pp.372-379
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• 2000

In this paper, we propose a fast variable-size block matching algorithm for motion estimation based on bit-pattern. Motion estimation in the proposed algorithm is performed after the representation of image sequence is transformed 8bit pixel values into 1bit ones depending on the mean value of search block, which brings a short searching time by reducing the computational complexity. Moreover, adaptive searching methods according to the motion information of the block make the procedure of motion estimation efficient by eliminating an unnecessary searching of low motion block and deepening a searching procedure in high motion block. Experimental results show that the proposed algorithm provides better performance-0.5dB PSNR improvement-than full search block matching algorithm with a fixed block size.

• Korean Institute of Interior Design Journal
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• v.17 no.5
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• pp.12-22
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• 2008

The purpose of this article is to establish fundamental sources and guidelines of bathroom designs of brand apartments in Korea. The article examines the current conditions of bathroom, satisfaction rates, and preference rates of residents in Mid-sized apartment units of the top five brand apartments based on construction capacity and brand popularity. A total of 427 samples, acquired via internet survey, were analyzed with the statistical computer program SPSS PC+ window version 15.0. The conclusions of the article are as follows: 1) Fixtures and products which fulfill various behaviors, as well as multi-functional space programming, are demanded. 2) Developing clear standards of basic bathroom fixtures and environments is also required in further research and to be applied to practical bathroom design. 3) The bathroom fixtures and environments ought to accommodate all age groups. 4) Respondents preferred a separated dry floor, either toilet or sink portion, to a full-dry or full-wet floor. 5) Respondents of all age groups considered bathroom as a private space, thus it should facilitate various private activities. The results of this study would contribute to adequate and sound bathroom design as key information.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.10
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• pp.4578-4589
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• 2011

The technologies of image acquisition, display, and storage of the breast have been developed in their specialized fields in recent years. The image acquisition system is a device that absorbs and stores images after examining breast tissue using X-ray. Due to the specificity and sensitivity of imaging, the early detection of breast cancer is feasible. In this paper, the current technologies for digital mammography are reviewed, and we propose a digital mammography and evaluate the performance of the implemented system.

• The Journal of Korea Robotics Society
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• v.11 no.3
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• pp.127-132
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• 2016

For a practical mobile robot team such as carrying out a search and rescue mission in a disaster area, the localization have to be guaranteed even in an environment where the network infrastructure is destroyed or a global positioning system (GPS) is unavailable. The proposed architecture supports localizing robots seamlessly by finding their relative locations while moving from a global outdoor environment to a local indoor position. The proposed schemes use a cooperative positioning system (CPS) based on the two-way ranging (TWR) technique. In the proposed TWR-based CPS, each non-localized mobile robot act as tag, and finds its position using bilateral range measurements of all localized mobile robots. The localized mobile robots act as anchors, and support the localization of mobile robots in the GPS-shadow region such as an indoor environment. As a tag localizes its position with anchors, the position error of the anchor propagates to the tag, and the position error of the tag accumulates the position errors of the anchor. To minimize the effect of error propagation, this paper suggests the new scheme of full-mesh based CPS for improving the position accuracy. The proposed schemes assuring localization were validated through experiment results.

• Journal of Environmental Impact Assessment
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• v.21 no.4
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• pp.567-572
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• 2012

This paper suggests the set-up plan of the assessment scope in road noise considering road characteristics with the prediction model of road noise. The RLS90 prediction model with some assumptions is used to establish the assessment scope of road noise. The main contents of the applied assumptions are smooth drive of cars, flat region, location of all noise sources in one lane, drive in design speed, and set-up of assessment scope according to traffic volume and car speed. The information of traffic volume to predict road noise is obtained by the distribution of small cars and full-sized cars in road. In this study, the total traffic volume in road is computed by adding the number of small cars to the conversion number of small cars, which means the number of small cars making the same noise as one full-sized car. The prediction result of road noise with the influence factor of traffic volume, car speed, distance between road and receiver is presented. The resultant assessment scope of road noise is obtained by combining road noise prediction data with the set-up standard of road noise assessment scope.