• Journal of Information Processing Systems
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• v.17 no.2
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• pp.385-398
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• 2021

The complexity of deep learning models affects the real-time performance of gesture recognition, thereby limiting the application of gesture recognition algorithms in actual scenarios. Hence, a residual learning neural network based on a deep convolutional neural network is proposed. First, small convolution kernels are used to extract the local details of gesture images. Subsequently, a shallow residual structure is built to share weights, thereby avoiding gradient disappearance or gradient explosion as the network layer deepens; consequently, the difficulty of model optimisation is simplified. Additional convolutional neural networks are used to accelerate the refinement of deep abstract features based on the spatial importance of the gesture feature distribution. Finally, a fully connected cascade softmax classifier is used to complete the gesture recognition. Compared with the dense connection multiplexing feature information network, the proposed algorithm is optimised in feature multiplexing to avoid performance fluctuations caused by feature redundancy. Experimental results from the ISOGD gesture dataset and Gesture dataset prove that the proposed algorithm affords a fast convergence speed and high accuracy.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.4
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• pp.161-168
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• 2003

We discuss the security of two famous password authenticated key exchange protocols, EKE2 and PAK. We introduce ′insider assisted attack′ Based on this assumption we point out weakness of the security of EKE2 and PAK protocols. More precisely, when the legitimate user wants to find other user′s password, called "insider-assisted attacker", the attacker can find out many ephemeral secrets of the server and then after monitoring on line other legitimate user and snatching some messages, he can guess a valid password of the user using the previous information. Of course for this kind of attack there are some constraints. Here we present a full description of the attack and point out that on the formal model, one should be very careful in describing the adversary′s behavior.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.9
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• pp.1241-1244
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• 2020

In this paper, we consider a downlink non-orthogonal multiple access system with a base station and N mobile stations, where we assume that instantaneous channel state information (CSI) is available at the base station. A power allocation scheme is proposed to achieve perfect fairness, which means equal data rates for all mobile stations. However, the power allocation scheme using full CSI requires high complexity. Hence, a simple power allocation scheme with low complexity is proposed by using high signal-to-noise power ratio (SNR) approximation. The simple power allocation scheme can achieve perfect fairness only for high SNR. However, it needs only the best CSI and the simple procedure to obtain power allocation coefficients. From simulation results, we show that the simple power allocation scheme provides remarkable fairness performance at high SNR.

• Journal of information and communication convergence engineering
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• v.20 no.1
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• pp.1-7
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• 2022

Herein, a new space-time block coding technique is proposed for a MIMO 2 × 2 multiple-input multiple output (MIMO) system to minimize the bit error rate (BER) in Rayleigh fading channels with reduced decoding complexity using ZF and MMSE linear detection techniques. The main objective is to improve the service quality of wireless communication systems and optimize the number of antennas used in base stations and terminals. The idea is to exploit the correlation product technique between both information symbols to transmit per space-time block code and their own orthogonal Walsh-Hadamard sequences to ensure orthogonality between both symbol vectors and create a full-rate orthogonal STBC code. Using 16 quadrature amplitude modulation and the quasi-static Rayleigh channel model in the MATLAB environment, the simulation results show that the proposed space-time block code performs better than the Alamouti code in terms of BER performance in the 2 × 2 MIMO system for both cases of linear decoding ZF and MMSE.

• Journal of Information Processing Systems
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• v.18 no.3
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• pp.389-401
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• 2022

The business of Internet of Vehicles (IoV) is growing rapidly, and the large amount of data exchange has caused problems of large mobile network communication delay and large energy loss. A strategy for resource allocation of IoV communication based on mobile edge computing (MEC) is thus proposed. First, a model of the cloud-side collaborative cache and resource allocation system for the IoV is designed. Vehicles can offload tasks to MEC servers or neighboring vehicles for communication. Then, the communication model and the calculation model of IoV system are comprehensively analyzed. The optimization objective of minimizing delay and energy consumption is constructed. Finally, the on-board computing task is coded, and the optimization problem is transformed into a knapsack problem. The optimal resource allocation strategy is obtained through genetic algorithm. The simulation results based on the MATLAB platform show that: The proposed strategy offloads tasks to the MEC server or neighboring vehicles, making full use of system resources. In different situations, the energy consumption does not exceed 300 J and 180 J, with an average delay of 210 ms, effectively reducing system overhead and improving response speed.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.333-336
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• 1997

In this paper, we present a nonlinear dynamic controller for position tracking of brushless dc motors. In constructing the controller, a backstepping-type approach is used under the condition of full state information, while an adaptive controller is adopted for parameter uncertainty throughout the entire electromechanical system. The nonlinear dynamic controller using the adaptive learning technique approach is shown to drive the state variables of system to the desired ones asymptotically and whose effectiveness is also sown via computer simulation.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.129-140
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• 1994

In this paper we investigate the hardware implementation of block matching algorithms (BMAs) for moving sequences. Using systolic arrays we propose a hardware architecture of a two-stage BMA using integral projections which reduces greatly computational complexity with its performance comparable to that of the full search (FS). Proposed hardware architecture is faster than hardware architecture of the FS by 2~15 times. For realization of the FS and two stage BMA modeling and simulation results using SPW and VHDL are also shown.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.31-39
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• 2001

W polymetal gate technology for giga bit DRAM are presented. Key module processes for polymetal gate are studied in detail. $W/WN_x/poly-silicon$ adopted for a word line of 256Mbit DRAM has good gate oxide integrity and junction leakage characteristics through full integration, which is comparable to those of conventional $WSi_x$/Poly-silicon gate process. These results undoubtedly show that $W/WN_x/poly-silicon$ is the strongest candidate as a word line for Giga bit DRAM.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.156-163
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• 1996

In this paper, we propose VLSI architectures for the full search block matching algorithm (FS BMA) and two-stage BMA using integral projections that reduce greatly computational complexity with its performance comparable to that of the FS BMA. The proposed VLSI architectures are faster than the conventional ones with lower hardware complexity. Also the proposed architectures of the FS BMA and two-stage BMA are modeled in VHDL and simulated to show their functional validity.