VLSI architectures for block matching algorithms using systolic arrays

시스톨릭 어레이를 이용한 블럭정합 알고리즘의 VLSI 구조

In this paper, we propose VLSI architectures for the full search block matching algorithm (FS BMA) and two-stage BMA using integral projections that reduce greatly computational complexity with its performance comparable to that of the FS BMA. The proposed VLSI architectures are faster than the conventional ones with lower hardware complexity. Also the proposed architectures of the FS BMA and two-stage BMA are modeled in VHDL and simulated to show their functional validity.