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A design of Direct Memory Access For H.264 Encoder (H.264 Encoder용 Direct Memory Access (DMA) 설계)

  • Jung, Il-Sub;Suh, Ki-Bum
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.10a
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    • pp.91-94
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    • 2008
  • The designed module save to memory after received Image from CMOS image Sensor(CIS), and set a motion of Encoder module, read from memory per one macroblock each original Image and reference image then supply or save. the time required 470 cycle when processed one macroblock. For designed construct verification, I develop reference Encoder C like JM 9.4 and I proved this module with test vector which achieved from reference encoder C.

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A Low Dynamic Power 90-nm CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling Scheme and Fast Motion Estimation Algorithm Called Adaptively Assigned Breaking-off Condition Search

  • Kobayashi, Nobuaki;Enomoto, Tadayoshi
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2009.01a
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    • pp.512-515
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    • 2009
  • A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage ($V_D$) and the optimum clock frequency ($f_c$) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to $31.5{\mu}W$, which was only 2.8% that of a conventional ME processor.

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One Chip 반향 제거기를 위한 알고리즘 개발에 관한 연구

  • 강정신;백인천;박상봉;박노경;차균현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.15 no.8
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    • pp.689-697
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    • 1990
  • This paper proposes ADAPTIVE STOCHASTIC ITERATION ALGORITHM that can be used for the full-duplex digital data transmission over existing twisted-pair cables. The canceller step size changes according to the residual echo level. Thus convergence speed increases by an order of magnitude over the conventional stochastic interation alogorithm. And it can be combined with the sequential type adaptive digital filter that simplifies the conventional echo canceller circuit. Thus it is suitable for LSI implementation. Theoretical analysis on two algorithms is carried out and the algorithm simulation program is developed.

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Timing Titter Analysis in the ISDN U-Interface (ISDN U-Interface에서 타이밍지터의 해석)

  • 김동관;이명수;강창언
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.13 no.5
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    • pp.369-378
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    • 1988
  • In this paper, the performance of the timing jitter which has great effects on the echo canceller that can be used for full-duplex digital transmission on two-wire subscriber loops is analyzed. The power spectrum of timing jitter is about 8.9dB lower in the AMI input format than in the Polar-NRZ-L input format. The performance of the echo canceller also has been shown improved by 4dB when the input signal is in the AMI format.

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A Fault-tolerant Task Scheduling Algorithm Supporting the Minimum Schedule Length (최소의 스케줄 길이를 유지하는 결함 허용 태스크 스케줄링 알고리즘)

  • Min, Byeong-Jun
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.4
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    • pp.1201-1210
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    • 2000
  • In order to tolerate faults which may occur during the execution of distributed tasks in high-performance parallel computer systems, tasks are duplicated on different processors. In this paper, by utilizing the task duplication based scheduling algorithm, a new task scheduling algorithm which duplicates each task on more than two different processors with the minimum schedule length is presented, and the number of processors required for the duplication is analyzed with the ratio of communication cost to computation time and the workload of the system. A simulation with various task graphs reveals that the number of processors required for the full-duplex fault-tolerant task scheduling with the obtainable minimum schedule length increases about 30% to 75% when compared with that of the task duplication based scheduling algorithm.

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A Study on Energy Harvesting Wireless Sensor Networks

  • Sharma, Pradip Kumar;Moon, Seo Yeon;Park, Jong Hyuk
    • Annual Conference of KIPS
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    • 2016.10a
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    • pp.199-201
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    • 2016
  • Wireless sensor networks offer an attractive solution to several environments, security, and process monitoring problems. However, one barrier for their full adoption is the need to provide electrical power over extended periods of time without the need of dedicated wiring. Energy harvesting offers good solutions to this problem in several applications. This paper surveys the energy requirements of typical sensor network nodes and summarizes the future research work in the field of energy harvesting resource allocation in wireless sensor networks.

Matching-based Advanced Integrated Diagnosis Method (매칭에 기반한 발전된 고장 진단 방법)

  • Lim, Yo-Seop;Kang, Sung-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.4A
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    • pp.379-386
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    • 2007
  • In this paper, we propose an efficient diagnosis algorithm for multiple stuck-at faults. Because of using vectorwise intersections as an important metric of diagnosis, the proposed diagnosis algorithm can diagnose multiple defects in single stuck-at fault simulator. In spite of multiple fault diagnosis, the number of candidate faults is drastically reduced. For identifying faults, the variable weight, positive calculations and negative calculations are used for the matching algorithm. To verify our algorithm, experiments were performed for ISCAS85 and full-scan version of ISCAS89 benchmark circuits.

Design and Implementation of a RFID Transponder Chip using CMOS Process (CMOS 공정을 이용한 무선인식 송수신 집적회로의 설계 및 제작)

  • 신봉조;박근형
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.10
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    • pp.881-886
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    • 2003
  • This paper describes the design and implementation of a passive transponder chip for RFID applications. Passive transponders do not have their own power supply, and therefore all power required for the operation of a passive transponder must be drawn from the field of the reader. The designed transponder consists of a full wave rectifier to generate a dc supply voltage, a 128-bit mask ROM to store the information, and Manchester coding and load modulation circuits to be used for transmitting the information from the transponder to the reader. The transponder with a size 410 x 900 ${\mu}$m$^2$ has been fabricated using 0.65 ${\mu}$m 2-poly, 2-metal CMOS process. The measurement results show the data transmission rate of 3.9 kbps at RF frequency 125 kHz.

A Study on Electronic Voting System Using Private Blockchain

  • Roh, Chang-Hyun;Lee, Im-Yeong
    • Journal of Information Processing Systems
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    • v.16 no.2
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    • pp.421-434
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    • 2020
  • The development of digital technology has changed the lives of many people in terms of the velocity and convenience of completing tasks. This technology has also been applied to the process of voting, yet electronic voting is seldom used. The existing electronic voting scheme operates by applying various encryption algorithms. This type of electronic voting can be problematic since the administrator is given full authority. The administrator cannot always be trusted, and the contents of the ballot could be forged or tampered by a single point of failure. To resolve these problems, researchers continue to apply blockchain technology to electronic voting. Blockchain technology provides reliability and data integrity because all untrusted network participants have the same data. In this paper, we propose an electronic voting system that secures reliability by applying blockchain technology to electronic voting and ensures secret voting.

The Efficient Query Evaluation Plan in the Spatial Database Engine

  • Liu, Zhao-Hong;Kim, Sung-Hee;Lee, Jae-Dong;Bae, Hae-Young
    • Proceedings of the Korean Information Science Society Conference
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    • 2001.04b
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    • pp.22-24
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    • 2001
  • A new GIS software Spatial Database Engine(SDE) has been developed to integrated with spatial database that combines conventional and spatially related data. As we known well in the traditional relation database system, the query evaluation techniques are a well-researched subject, many useful and efficient algorithms have been proposed, but in the spatial database system, it is a litter difference with the traditionally ones. Based on the Query Graph Model(QGM), we implemented our own query evaulation plan in the SDE, which can deal with the full functionality query statement SELECT-FROM-WHERE_GROUPBY-HAVING, and treat the spatial data and non-spatial data seamlessly. We proposed a novel multi way join algorithm base on nest loop that may be attractive.

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