• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.59-64
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• 2011

A low noise and low power RF front-end for 5.8 GHz DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 GHz LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 ${\mu}m$ CMOS process and draws 7.3 mA from a 1.2 V supply voltage. It shows a voltage gain of 40 dB and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.894-897
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• 2003

Recently, the rapid growth of mobile radio system has led to an increasing demand of low-cost high performance communication IC's. In this paper, we have designed RF front end for wireless LAN receiver employ zero-IF architecture. A low-noise amplifier (LNA) and double-balanced mixer is included in a front end. The zero-IF architecture is easy to integrate and good for low power consumption, so that is coincided to requirement of wireless LAN. But the zero-IF architecture has a serious problem of large offset. Image-reject mixer is a good structure to solve offset problem. Using offset compensation circuit is good structure, too. The front end is implemented in 0.25 ${\mu}m$ CMOS technology. The front end has a noise figure of 5.6 dB, a power consumption of 16 mW and total gain of 22 dB.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.11
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• pp.61-68
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• 2008

In this paper, we propose a RF front-end developments for vehicle UWB radar systems. UWB systems have a very narrow pulse width that is below 1ns. Therefore, UWB is designed to have broadband quality of low power several GHz and must coexist with the radio communication system. UWB's advantages include high channel capacity and data rate, because precise resolution for multi-path can easily position estimate and Rake receiver. Also, UWB has low interference because it displays broadband quality of low power. Positioning is made possible by short range accuracy, which can reduce the expense of system design. An RF front-end module is designed using the DCR(Direct ConveRsion) method and is composed in RF for vehicles at a low-cost.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.49-55
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• 2013

A high-voltage highly-integrated analog front-end (AFE) IC for medical ultrasound imaging applications is implemented using standard 0.18-${\mu}m$ CMOS process. The proposed AFE IC is composed of a high-voltage (HV) pulser utilizing stacked transistors generating up to 15 Vp-p pulses at 2.6 MHz, a low-voltage low-noise transimpedance preamplifier, and a HV switch for isolation between the transmit and receive parts. The designed IC consumes less than $0.15mm^2$ of core area, making it feasible to be applied for multi-array medical ultrasound imaging systems, including portable handheld applications.

• Journal of Construction Engineering and Project Management
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• v.3 no.2
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• pp.1-12
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• 2013

Research indicates that good front-end planning (FEP) results in the achievement of higher levels of project performance. By facilitating collaboration among stakeholders in diverse locations with the use of workflow-enabled processes, such pressures can be reduced, and the overall process and results of FEP can be improved. With these goals, a front-end planning tool (FEPT) has been developed as support for owners and major contractors who are engaged in front-end planning. This paper presents the new FEPT and describes how it has been used for construction megaprojects in the nuclear power, oil and gas, and mining industries. The paper begins with the definitions related to and an explanation of the general process for implementing and applying the FEPT and then describes and analyzes how the FEPT was applied in case study projects in order to test its validity. The results indicate that the FEPT increases the efficiency and effectiveness of front-end planning for the megaprojects studied and that it has the potential to produce similar results for other megaprojects.

• Journal of Electrical Engineering and Technology
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• v.5 no.4
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• pp.571-579
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• 2010

This paper reviews and analyzes converters for SRM(Switched Reluctance Motor) drive. Conventional classification focuses on the number of power switches and diodes. It is easy to find the number of semiconductors and the cost by counting the number of active components, but it does not show the important characteristics of a power converter. The voltage ratings for the power switches and diodes are also difficult to identify. This paper proposes a switched reluctance (SR) converter configuration that is classified based on the commutation type and magnetic energy path. The converter has three parts: utility interface, front-end circuit, and power converter. Based on the overview on the conventional SR drive, the most important characteristic of the converter is determined by the topology of front-end in conjunction with the power converter. An SR converter has two parts: front-end and power converter. Inasmuch as the capacitive front-end is widely used for voltage source converters, this paper focuses on topologies for the front-end.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1009-1014
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• 2012

This paper has proposed a 2,500 MHz ~ 2,570 MHz 0.13-${\mu}m$ CMOS RF front-end transmitter for LTE-Advanced systems. The proposed RF front-end transmitter is composed of a quadrature up-conversion mixer and a driver amplifier. The measurement results show the maximum output power level is +6 dBm and the suppression ratio for the image sideband and LO leakage are better than -40 dBc respectively. The fabricated chip consumes 36 mA from a 1.2 V supply voltage.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1819-1829
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• 2018

A three-phase, three-switch, and three-level boost-type PWM rectifier (Vienna rectifier) is proposed as an active front-end power factor correction (PFC) rectifier for telecom loads. The proposed active front-end PFC rectifier system is modeled by the switching cycle average model. The relation between duty ratios and DC link capacitor voltages is derived in terms of the system input currents. Furthermore, the feasible switching states are identified and applied to the proposed system to reduce the switching stress and DC ripples. A detailed equivalent circuit analysis of the proposed front-end PFC rectifier is conducted, and its performance is verified through simulations in MATLAB. Simulation results are verified using an experimental setup of an active front-end PFC rectifier that was developed in the laboratory. Simulation and experimental results demonstrate the improved power quality parameters that are in accordance with the IEEE and IEC standards.

• Journal of the Korea Convergence Society
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• v.10 no.1
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• pp.13-24
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• 2019

Each company has different business processes. Since it is impossible that an ERP system contains every different business processes, the productivity of customizing and maintenance well-matched for the business process of a company is the key to successful implementation. This ERP UI development tool was developed for better connection to back-end in terms of customizing and maintenance, integration with design, providing various tools for higher productivity, reusability, and standardized user interface so that it enhances the productivity, meets the UI standard, and copes with upcoming changes of business process. In the further study, the study on the service automation and integrated development environment with front-end and back-end providing through the advanced user convenience development for front-end designer and front-end generator would be carried out.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.3
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• pp.183-189
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• 2009

In this paper, we propose RF front-end architecture using hybrid conversion method to receive broadband signal. The validity is verified by design, fabrication and experiment. The proposed RF front-end architecture due to up-conversion block improves the deficiency of performance deterioration to be generated through harmonic signal and image signal conversion in the conventional RF front-end, and improves the deficiency of the complexity that is from to adopt a multiple local oscillators for the generation of wideband LO signal in the conventional RF front-end by applying the principle that tuning bandwidth is multiplied at sub-harmonic mixer. Manufactured circuits satisfy the deduced design specification and target standard with gain above 80 dB, noise figure below 6.0 dB and IIP3 performance above -5.0 dBm for the condition of the minimum gain in RF front-end.