• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.179-192
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• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.151-158
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• 2002

In this paper, Phase locked microwave oscillator having the low phase noise and high stability for digital MMDS down converter was designed. we have been analyzed the low phase noise properties by the active device nonlinear equivalent circuits and derived the necessary and sufficient conditions for high stable voltage control oscillator. And it is applied to phase locked loop, we design the phase locked microwave oscillator of frequency synthesizer. Experimental results of designed phase locked oscillator shows -85dBc/Hz @ 10KHz phase noise properties and simulation result is -90Bc/Hz @ 10kHz respectively we shows that proposed low phase noise and stable conditions of phase locked microwave oscillator can be applied to design the high stable digital MMDS frequency synthesizer.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.368-371
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• 2000

The PLL(Phase-Locked Loop) techniques re employed to make the switching frequency of a resonant inverter follow the resonant frequency which may vary due to the load variations during operation. The conventional design guide of PLL is not suitable in these case since the inverter characteristics are not considered. In this paper the phase characteristics of a resonant inverter is analysed and added to the closed loop. And the design of PLL with digital phase detector is illustrated for the output frequency to track the resonant frequency of the inverter.

• International Journal of Control, Automation, and Systems
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• v.5 no.2
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• pp.161-169
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• 2007

The PLL equivalent augmented system incorporated with state feedback is proposed in this paper. The optimal value of filter time constant of loop filter in the phase-locked loop control system and the optimal state feedback gain designed by using linear quadratic regulator approach are derived. This approach allows the PLL control system to employ the large value of the phase-frequency gain $K_d$ and voltage control oscillator gain $K_o$. In designing, the structure of phase-locked loop control system will be rearranged to be a phase-locked loop equivalent augmented system by including the structure of loop filter into the process and by considering the voltage control oscillator as an additional integrator. The designed controller consisting of state feedback gain matrix K and integral gain $k_1$ is an optimal controller. The integral gain $k_1$ related to weighting matrices q and R will be an optimal value for assigning the filter time constant of loop filter. The experimental results in controlling the second-order lag pressure process using two types of loop filters show that the system response is fast without steady-state error, the output disturbance effect rejection is fast and the tracking to step changes is good.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2444-2450
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• 2011

In this paper, we propose the low fractional spur phase-locked loop(PLL) with multiple phase-frequency detector(PFD). The fractional spurs are suppressed by using a new PFD. The new PFD architecture with two different edge detection methods is used to suppress the fractional spur by limiting a maximum width of the output signals of PFD. The proposed PLL was simulated by HSPICE using a 0.35m CMOS parameters. The simulation results show that the proposed PLL is able to suppress fractional spurs with fast locking.

• Journal of Power Electronics
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• v.13 no.5
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• pp.884-895
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• 2013

In this paper, the Fourier-based PLL (Phase-locked Loop) is introduced with a new structure, capable of selective harmonic detection in single and three-phase systems. The application of the FB-PLL to harmonic detection is discussed and a new model applicable to three-phase systems is introduced. An analysis of the convergence of the FB-PLL based on a linear model is presented. Simulation and experimental results are included for performance analysis and to support the theoretical development. The decomposition of an input signal in its harmonic components using the Fourier theory is based on previous knowledge of the signal fundamental frequency, which cannot be easily implemented with input signals with varying frequencies or subjected to phase-angle jumps. In this scenario, the main contribution of this paper is the association of a phase-locked loop system, with a harmonic decomposition and reconstruction method, based on the well-established Fourier theory, to allow for the tracking of the fundamental component and desired harmonics from distorted input signals with a varying frequency, amplitude and phase-angle. The application of the proposed technique in three-phase systems is supported by results obtained under unbalanced and voltage sag conditions.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.4
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• pp.356-363
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• 2004

This paper presents a precision voltage control technique of a single phase PWM inverter for a constant voltage and constant frequency(CVCF) applications. The proposed control scheme employs an additional phase-locked loop(PLL) compensator which is constructed using the output capacitor voltage and current. The computer simulation and experiment are carried out for the actual single-phase PWM inverter and it is well demonstrated from these results that the steady-state performance and total harmonic distortion(THD) are remarkably improved by employing the proposed technique.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.777-786
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• 2003

The phase noise characteristics of the phase-locked loop frequency synthesizer were predicted based on the analysis for phase noise contribution of noise sources. The proposed phase noise model in this paper more accurately predicts the phase noise spectrum of frequency synthesizer. To accurately model the phase noise contribution of noise sources in frequency synthesizer, the phase noise sources were analyzed via modeling of the frequency divider and phase noise components using Leeson model for reference signal source and VCO. The phase noise transfer functions to VCO from noise sources were analyzed by superposition theory and linear operation of phase-locked loop. To evaluate the phase noise prediction model, the frequency synthesizers were fabricated and were evaluated by measured data and prediction data.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.2
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• pp.417-426
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• 2000

In this paper, CE-CPSK(Constant Envelope Continuous Phase Shift Keying) modulated DS/SS(Direct Sequence Spread Spectrum) transceiver with 908 MHz carrier frequency and 1.5 MHz PN clock rate is proposed. To overcome the effect of nun-linear power amplifier, CE-CPSK modulation method which has the constant envelope and continuous phase characteristics is proposed. To analyze the DS/SS receiver performance with respect to code tracking loop, multipath fading channel is characterized as a two-ray Rayleigh fading channel. To compensate the demerit of analog delay locked loop, digital delay locked loop is employed for code tracking loop. Simulation and experimental examination has been carried out in AWGN(Additive White Gaussian Noise) and Rayleigh fading channel environment in order to prove validity of the proposed method.