• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.7
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• pp.1331-1338
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• 2011

This paper proposes a method for frequency control of islanded microgrid with battery energy storage system. For frequency control of islanded microgrid, battery energy storage system uses a phase locked loop algorithm with positive sequence components for a fast frequency estimation. Microgrid is a power system with small inertia because it has small capacity generators and inverter systems for renewable energy. So, Islanded microgrid's frequency varies fast and large as small generation and load changes. To reduce frequency variation of islanded microgrid, it needs a device with fast frequency response. For fast frequency response, a fast frequency tracking is important. To show the validation of proposed fast frequency tracking algorithm, battery energy storage system with proposed algorithm is tested in microgrid pilot plant.

• Journal of the Korea Institute of Military Science and Technology
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• v.17 no.5
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• pp.629-636
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• 2014

In the proposed paper, we designed low phase noise frequency synthesizer for Ku-band. The proposed up-mixing frequency synthesizer consists of narrow local oscillation part and variable frequency oscillation part. To improve the phase noise of frequency synthesizer, we analyze how the configuration of frequency synthesizer affect the phase noise. The implemented frequency synthesizer reduce the phase noise. The phase noise is -95.18dBc/Hz at 7kHz frequency offset in 16GHz and -94.27dBc/Hz at 7kHz frequency offset in 16.125GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.194-200
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• 2003

In this paper, FSK(Frequency Shift Keying) demodulator which is widely used for FH-SS system is designed and the experimental results are analyzed. The performance of the ADPLL(All-digital Phase-Locked-Loop), which is the main part of the demodulator circuit, is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the ADPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. There is about 2${\mu}\textrm{s}$ difference in time constant of the PLL. This difference is not critical in the demodulator. And the experimental results show that the transmitted data is well demodulated when the phase difference between the FSK modulated signal and the reference signal is about 180 degree.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.99-106
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• 2012

For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phase-locked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on $V_{ctrl}$ induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 nm CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 MHz output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.43-49
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• 2000

We proposed ADD(Alternate Directional Delay) circuit technique as the DLL(Delay Locked Loop) circuits which technique is established the data valid window(tDV) in DDR(Double Data Rate) Synchronous DRAM. This technique could be decrease area-overhead which it could generated bidirectional clock simultaneously using only one delay chain block. In this paper for high speed memory with relatively small size. This technique decreased area-overhead more 2 times than SMD(Synchronous Mirror Delay) technique. ADD technique has 50ps-140ps jitter and the operation frequency has 166MHz-66MHz range.(at 2.5V, TYP. condition)

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.9
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• pp.1692-1701
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• 1994

Macromodeling technology is useful to simulate and analyze the performance of new elements and complicated circuits or systems without any changes in today's general simulator, PSPICE. In this paper, Phase Locked Loop(PLL) is designed using macromodeling technique. The PLL macromodel has two basic sub-macromodels of the phase detector and the voltage controlled oscillator(VCO). The PLL macromodel has two open terminals for inserting RC low pass filter. The PLL macromodel is simulated using simulation parameters of LM565CN manufactured in the National company. At a free-running frequency, 2500Hz, upper lock range and lower capture range was 437Hz, 563Hz, respectively. Also, experimental results and simulation results of LM565CN PLL show good agreement.

• Journal of Power Electronics
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• v.15 no.2
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• pp.419-430
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• 2015

Flux estimation is a significant foundation of high-performance control for DC-excited synchronous motor. For almost all flux estimators, such as the flux estimator based on phase locked loop (PLL), DC drift causes fluctuations in flux magnitude. Furthermore, significant dynamic error may be introduced at transient conditions. To overcome these problems, this paper proposes an improved flux estimator for the PLL-based algorithm. Filters based on the generalized integrator are used to avoid flux fluctuation problems caused by the DC drift at the back electromotive force. Programmable low-pass filters are employed to improve the dynamic performance of the flux estimator, and the cutoff frequency of the filter is determined by the dynamic factor. The algorithm is verified by a 960V/1.6MW industrial prototype. Simulation and experimental results show that the proposed estimator can estimate the flux more accurately than the PLL-based algorithm in a cycloconverter-fed DC-excited synchronous machine vector control system.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.39-49
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• 1999

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.10a
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• pp.28-34
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• 1986

The frequency synthesizer for Fast Frequency Hopping System musy be capable of a fast tuning with a small step frequency over wide band. The most conventional frequency synthesizer that uses the phase locked loop (PLL) enables the wide band problem but have a poor side of the low resolution and the transient response. In this paper, we have discussed the experimental results of a direct digital frequency synthesizer which can be applicable to the Fast Frequency Hopping System, using digital-to-analoq (D/A)conversion techniques. With this system we can find the merits of a fine resolution and the possibility of a fast tuning leaving the problems of transent frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.137-144
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• 2013

A delay-locked loop (DLL) that generates a 32-phase clock with the operating frequency of 125 MHz is introduced. The proposed DLL uses a delay line of $4{\times}8$ matrix architecture to improve a differential non-linearity (DNL) of the delay line. Furthermore, a integral non-linearity (INL) of the proposed DLL is improved by calibrating phases of clocks that is supplied to four points of an input stage of the $4{\times}8$ matrix delay line. The proposed DLL is fabricated by using $0.11-{\mu}m$ CMOS process with a 1.2 V supply. The measured operating frequency range of the implemented DLL is 40 MHz to 280 MHz. At the operating frequency of 125MHz, the measurement results shows that the DNL and INL are +0.14/-0.496 LSB and +0.46/-0.404 LSB, respectively. The measured peak-to-peak jitter of the output clock is 30 ps when the peak-to-peak jitter of the input clock is 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW, respectively.