• Title/Summary/Keyword: flash memory device

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A Mapping Table Caching Scheme for NAND Flash-based Mobile Storage Devices (NAND 플래시 기반 모바일 저장장치를 위한 사상 테이블 캐싱 기법)

  • Yang, Soo-Hyeon;Ryu, Yeon-Seung
    • The Journal of Society for e-Business Studies
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    • v.15 no.4
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    • pp.21-31
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    • 2010
  • Recently e-business such as online financial trade and online shopping using mobile computes are widely spread. Most of mobile computers use NAND flash memory-based storage devices for storing data. Flash memory storage devices use a software called flash translation layer to translate logical address from a file system to physical address of flash memory by using mapping tables. The legacy FTLs have a problem that they must maintain very large mapping tables in the RAM. In order to address this issues, in this paper, we proposed a new caching scheme of mapping tables. We showed through the trace-driven simulations that the proposed caching scheme reduces the space overhead dramatically but does not increase the time overhead. In the case of online transaction workload in e-business environment, in particular, the proposed scheme manifests better performance in reducing the space overhead.

A File Clustering Algorithm for Wear-leveling (마모도 평준화를 위한 File Clustering 알고리즘)

  • Lee, Taehwa;Cha, Jaehyuk
    • Journal of Digital Contents Society
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    • v.14 no.1
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    • pp.51-57
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    • 2013
  • Storage device based on Flash Memory have many attractive features such as high performance, low power consumption, shock resistance, and low weight, so they replace HDDs to a certain extent. An Storage device based on Flash Memory has FTL(Flash Translation Layer) which emulate block storage devices like HDDs. A garbage collection, one of major functions of FTL, effects highly on the performance and the lifetime of devices. However, there is no de facto standard for new garbage collection algorithms. To solve this problem, we propose File Clustering Algorithm. File Clustering Algorithm respect to update page from same file at the same time. So, these are clustered to same block. For this mechanism, We propose Page Allocation Policy in FTL and use MIN-MAX GAP to guarantee wear leveling. To verify the algorithm in this paper, we use TPC Benchmark. So, The performance evaluation reveals that the proposed algorithm has comparable result with the existing algorithms(No wear leveling, Hot/Cold) and shows approximately 690% improvement in terms of the wear leveling.

Performance Evaluation of SSD-Index Maintenance Schemes in IR Applications

  • Jin, Du-Seok;Jung, Hoe-Kyung
    • Journal of information and communication convergence engineering
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    • v.8 no.4
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    • pp.377-382
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    • 2010
  • With the advent of flash memory based new storage device (SSD), there is considerable interest within the computer industry in using flash memory based storage devices for many different types of application. The dynamic index structure of large text collections has been a primary issue in the Information Retrieval Applications among them. Previous studies have proven the three approaches to be effective: In- Place, merge-based index structure and a combination of both. The above-mentioned strategies have been researched with the traditional storage device (HDD) which has a constraint on how keep the contiguity of dynamic data. However, in case of the new storage device, we don' have any constraint contiguity problems due to its low access latency time. But, although the new storage device has superiority such as low access latency and improved I/O throughput speeds, it is still not well suited for traditional dynamic index structures because of the poor random write throughput in practical systems. Therefore, using the experimental performance evaluation of various index maintenance schemes on the new storage device, we propose an efficient index structure for new storage device that improves significantly the index maintenance speed without degradation of query performance.

Technology of MRAM (Magneto-resistive Random Access Memory) Using MTJ(Magnetic Tunnel Junction) Cell

  • Park, Wanjun;Song, I-Hun;Park, Sangjin;Kim, Teawan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.2 no.3
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    • pp.197-204
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    • 2002
  • DRAM, SRAM, and FLASH memory are three major memory devices currently used in most electronic applications. But, they have very distinct attributes, therefore, each memory could be used only for limited applications. MRAM (Magneto-resistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. To be a commercially competitive memory device, scalability is an important factor as well. This paper is testing the actual electrical parameters and the scaling factors to limit MRAM technology in the semiconductor based memory device by an actual integration of MRAM core cell. Electrical tuning of MOS/MTJ, and control of resistance are important factors for data sensing, and control of magnetic switching for data writing.

MNFS: Design of Mobile Multimedia File System based on NAND FLASH Memory (MNFS : NAND 플래시메모리를 기반으로 하는 모바일 멀티미디어 파일시스템의 설계)

  • Kim, Hyo-Jin;Won, You-Jip;Kim, Yo-Hwan
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.11
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    • pp.497-508
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    • 2008
  • Mobile Multimedia File System, MNFS, is a file system which extensively exploits NAND FLASH Memory, Since general Flash file systems does not precisely meet the criteria of mobile devices such as MP3 Player, PMP, Digital Camcorder, MNFS is designed to guarantee the optimal performance of FLASH Memory file system. Among many features MNFS provides, there are three distinguishable characteristics. MNFS guarantees, first, constant response time in sequential write requests of the file system, second, fast file system mounting time, and lastly least memory footprint. MNFS implements four schemes to provide such features, Hybrid mapping scheme to map file system metadata and user data, manipulation of user data allocation to fit allocation unit of file data into allocation unit of NAND FLASH Memory, iBAT (in core only Block Allocation Table) to minimize the metadata, and bottom-up representation of directory. Prototype implementation of MNFS was tested and measured its performance on ARM9 processor and 1Gbit NAND FLASH Memory environment. Its performance was compared with YAFFS, NAND FLASH File system, and FAT file system which use FTL. This enables to observe constant request time for sequential write request. It shows 30 times faster mounting time to YAFFS, and reduces 95% of HEAP memory consumption compared to YAFFS.

High Efficiency Life Prediction and Exception Processing Method of NAND Flash Memory-based Storage using Gradient Descent Method (경사하강법을 이용한 낸드 플래시 메모리기반 저장 장치의 고효율 수명 예측 및 예외처리 방법)

  • Lee, Hyun-Seob
    • Journal of Convergence for Information Technology
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    • v.11 no.11
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    • pp.44-50
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    • 2021
  • Recently, enterprise storage systems that require large-capacity storage devices to accommodate big data have used large-capacity flash memory-based storage devices with high density compared to cost and size. This paper proposes a high-efficiency life prediction method with slope descent to maximize the life of flash memory media that directly affects the reliability and usability of large enterprise storage devices. To this end, this paper proposes the structure of a matrix for storing metadata for learning the frequency of defects and proposes a cost model using metadata. It also proposes a life expectancy prediction policy in exceptional situations when defects outside the learned range occur. Lastly, it was verified through simulation that a method proposed by this paper can maximize its life compared to a life prediction method based on the fixed number of times and the life prediction method based on the remaining ratio of spare blocks, which has been used to predict the life of flash memory.

Improvement of Current Path by Using Ferroelectric Material in 3D NAND Flash Memory (3D NAND Flash Memory에 Ferroelectric Material을 사용한 Current Path 개선)

  • Jihwan Lee;Jaewoo Lee;Myounggon Kang
    • Journal of IKEEE
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    • v.27 no.4
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    • pp.399-404
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    • 2023
  • In this paper, we analyzed the current path in the O/N/O (Oxide/Nitride/Oxide) structure of 3D NAND Flash memory and in the O/N/F (Oxide/Nitride/Ferroelectric) structure where the blocking oxide is replaced by a ferroelectric. In the O/N/O structure, when Vread is applied, a current path is formed on the backside of the channel due to the E-fields of neighboring cells. In contrast, the O/N/F structure exhibits a current path formed on the front side due to the polarization of the ferroelectric material, causing electrons to move toward the channel front. Additionally, we performed an examination of device characteristics considering channel thickness and channel length. The analysis results showed that the front electron current density in the O/N/F structure increased by 2.8 times compared to the O/N/O structure, and the front electron current density ratio of the O/N/F structure was 17.7% higher. Therefore, the front current path is formed more effectively in the O/N/F structure than in the O/N/O structure.

Workload-Driven Adaptive Log Block Allocation for Efficient Flash Memory Management (효율적 플래시 메모리 관리를 위한 워크로드 기반의 적응적 로그 블록 할당 기법)

  • Koo, Duck-Hoi;Shin, Dong-Kun
    • Journal of KIISE:Computer Systems and Theory
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    • v.37 no.2
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    • pp.90-102
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    • 2010
  • Flash memory has been widely used as an important storage device for consumer electronics. For the flash memory-based storage systems, FTL (Flash Translation Layer) is used to handle the mapping between a logical page address and a physical page address. Especially, log buffer-based FTLs provide a good performance with small-sized mapping information. In designing the log buffer-based FTL, one important factor is to determine the mapping structure between data blocks and log blocks, called associativity. While previous works use static associativity fixed at the design time, we propose a new log block mapping scheme which adjusts associativity based on the run-time workload. Our proposed scheme improves the I/O performance about 5~16% compared to the static scheme by adjusting the associativity to provide the best performance.

Index management technique using Small block in storage device based on NAND flash memory

  • Lee, Seung-Woo;Oh, Se-Jin
    • Journal of the Korea Society of Computer and Information
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    • v.25 no.10
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    • pp.1-14
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    • 2020
  • In this paper, we propose to solve the problem of increasing system memory usage due to an increase in the number of mapping information management when using a NAND flash memory-based storage device in an existing sector-based file system. The proposed technique is to store only mapping information in page units based on index blocks and manage them in block units. To this end, the proposed technique uses a sequential offset for storing and managing a plurality of mapping information in one page in a small block, and a reverse offset for a spare page corresponding to a change in mapping information in the block. Through this, the proposed technique has the advantage that the number of block-unit deletions is less than that of the existing technique, and the system memory usage required for mapping information management is low. Reduced by about 32%.

A Memory Mapping Technique to Reduce Data Retrieval Cost in the Storage Consisting of Multi Memories (다중 메모리로 구성된 저장장치에서 데이터 탐색 비용을 줄이기 위한 메모리 매핑 기법)

  • Hyun-Seob Lee
    • Journal of Internet of Things and Convergence
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    • v.9 no.1
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    • pp.19-24
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    • 2023
  • Recently, with the recent rapid development of memory technology, various types of memory are developed and are used to improve processing speed in data management systems. In particular, NAND flash memory is used as a main media for storing data in memory-based storage devices because it has a nonvolatile characteristic that it can maintain data even at the power off state. However, since the recently studied memory-based storage device consists of various types of memory such as MRAM and PRAM as well as NAND flash memory, research on memory management technology is needed to improve data processing performance and efficiency of media in a storage system composed of different types of memories. In this paper, we propose a memory mapping scheme thought technique for efficiently managing data in the storage device composed of various memories for data management. The proposed idea is a method of managing different memories using a single mapping table. This method can unify the address scheme of data and reduce the search cost of data stored in different memories for data tiering.