• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.87-96
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• 2019

Low power issue is one of the most critical problems in the Internet of Things (IoT), which are powered by battery. To solve this problem, various approaches have been presented so far. In this paper, we propose a method to reduce the power consumption by reducing the numbers of accesses into the flash memory consuming a large amount of power for on-chip software execution. Our approach is based on using cooperative logging structure to distribute the sampling overhead in single sensor node to adjacent nodes in case of rare-event applications. The proposed algorithm to identify event occurrence is newly introduced with negative feedback method by observing difference between past data and recent data coming from the sensor. When an event with need of flash access is determined, the proposed approach only allows access to write the sampled data in flash memory. The proposed event detection algorithm (EDA) result in 30% reduction of power consumption compared to the conventional flash write scheme for all cases of event. The sampled data from the sensor is first traced into the random access memory (RAM), and write access to the flash memory is delayed until the page buffer of the on-chip flash memory controller in the micro controller unit (MCU) is full of the numbers of the traced data, thereby reducing the frequency of accessing flash memory. This technique additionally reduces power consumption by 40% compared to flash-write all data. By sharing the sampling information via LoRa channel, the overhead in sampling data is distributed, to reduce the sampling load on each node, so that the 66% reduction of total power consumption is achieved in several IoT edge nodes by removing the sampling operation of duplicated data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.533-536
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• 2004

In this paper, CMOS A/D converter with 10bit 32MSPS at 3.3V is designed for HPNA 2.0. In order to obtain the resolution of 10bit and the character of high-speed operation, we present multi-stage type architecture. That consist of sample and hold(S&H), 4bit flash ADC and 4bit Multiplier D/A Converter (MADC) also the Overflow and Underflow for timing error correct of Digital Correct ion Logic (DCL). The proposed ADC is based on 0.35um 3-poly 5-metal N-well CMOS technology. and it consumes 130mW at 3.3V power supply.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.30-39
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• 1994

A 1-chip high quality binarizing VLSI image processor (which has 8 bit ADC. 6 bit flash ADC, 15K standard cell, and 1K word ROM) based on 10 MIPS 16 bit DSP is implemented for FAX. This image processor(IP) performs image pre-processing. image quality improvement in copying and sending mode, and mixed image processing based on the fuzzy theory. And smoothing in sub-scan direction is applied for normal receiving mode data so the received data is enhanced like fine mode data. Each algorithm is processed with the same type of image processing window and 2-D image processing is implemented with a 1-D line buffer. The fabricated chip is applied to a FAX machine and image quality improvement is verified.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.473-473
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• 2000

This paper presents the 2-bit parallel algorithmic ADC using current mode for parallel method algorithm. It is operated by parallel conversion, 2-bit at each moment, and increase bit numbers by serial connection. The circuit operates in current mode. The comparison ratio can be controlled while working under mode operation. The circuit design used 0.8 ${\mu}{\textrm}{m}$ CMOS technology which capable to convert 2-bit in 50 ns, power consumed 0.786 nW, with input current 0-50 mA from 3V single supply. From simulation testing, the conversion rate is much faster than other method.

• Journal of Biomedical Engineering Research
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• v.27 no.5
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• pp.203-209
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• 2006

The aim of this study is to investigate the feasibility of ex vivo MR diffusion tensor imaging technique in order to observe the diffusion-contrast characteristics of human gastric tissues. On normal and pathologic gastric tissues, which have been fixed in a polycarbonate plastic tube filled with 10% formalin solution, laboratory made 3D diffusion tensor Turbo FLASH pulse sequence was used to obtain high resolution MR images with voxel size of $0.5{\times}0.5{\times}0.5mm^3\;using\;64{\times}32{\times}32mm^3$ field of view in conjunction with an acquisition matrix of $128{\times}64{\times}64$. Diffusion weighted- gradient pulses were employed with b values of 0 and $600s/mm^2$ in 6 orientations. The sequence was implemented on a clinical 3.0-T MRI scanner(Siemens, Erlangen, Germany) with a home-made quadrature-typed birdcage Tx/Rx rf coil for small specimen. Diffusion tensor values in each pixel were calculated using linear algebra and singular value decomposition(SVD) algorithm. Apparent diffusion coefficient(ADC) and fractional anisotropy(FA) map were also obtained from diffusion tensor data to compare pixel intensities between normal and abnormal gastric tissues. The processing software was developed by authors using Visual C++(Microsoft, WA, U.S.A.) and mathematical/statistical library of GNUwin32(Free Software Foundation). This study shows that 3D diffusion tensor Turbo FLASH sequence is useful to resolve fine micro-structures of gastric tissue and both ADC and FA values in normal gastric tissue are higher than those in abnormal tissue. Authors expect that this study also represents another possibility of gastric carcinoma detection by visualizing diffusion characteristics of proton spins in the gastric tissues.

• Journal of Sensor Science and Technology
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• v.14 no.4
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• pp.272-277
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• 2005

A CMOS active pixel sensor has been designed and fabricated using standard 2-poly and 4-metal $0.35{\mu}m$ CMOS processing technology. The CMOS active pixel sensor has been made up of a unit pixel having a highly sensitive PMOSFET photo-detector and electronic shutters that can control the light exposure time to the PMOSFET photo-detector, correlated-double sampling (CDS) circuits, and an 8-bit two-step flash analog to digital converter (ADC) for digital output. This sensor can obtain a stable photo signal in a wide range of light intensity. It can be realized with a special function of an electronic shutter which controls the light exposure-time in the pixel. Moreover, this sensor had obtained the digital output using an embedded ADC for the system integration. The designed and fabricated image sensor has been implemented as a $128{\times}128$ pixel array. The area of the unit pixel is $7.60{\mu}m{\times}7.85{\mu}m$ and its fill factor is about 35 %.

• Journal of IKEEE
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• v.19 no.1
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• pp.52-57
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• 2015

The disease diagnosis system has been developed using the thin nitride(Si3N4) cantilever arrays which can measure the difference of capacitances between sensor and reference. The system consists of 32-bits RISC(Reduced Instruction Set Computer), RAM/Flash, bus, communication IP's, ADC(Analog Digital Converter) board, and LCD display. The marker selection method, which give us the good accuracy from reasonal numbers of markers, is suggested. The developed system has the resolution under 1fF and can detect 10nM concentration of Thrombin.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.126-134
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• 1990

In order to implement high-speed data acquistion system in CMOS VLSI technology, means must be found to overcome the relatively low transconductance and large device mismatch characteristic of MOS device. Because of these device limitations, circuit design approaches tradition-ally used in high-speed bipolar analog-to-digital converter(ADC) are suited to CMOS implementation. Also the design of VLSI CMOS comparator wherein voltage comparision is accomplished by means of a pipelined cascade RSA (Regenerative Sense Amplifier). So, in this paper we designed the A/D converter incorporates the pipelined CMOS comparator.