• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.131-131
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• 2008

Silicon carbide (SiC) has attracted significant attention for high frequency, high temperature and high power devices due to its superior properties such as the large band gap, high breakdown electric field, high saturation velocity and high thermal conductivity. We performed Al ion implantation processes on n-type 4H-SiC substrate using a SILVACO ATHENA numerical simulator. The ion implantation model used a Monte-Carlo method. We studied the effect of channeling by Al implantation simulation in both 0 off-axis and 8 off-axis n-type 4H-SiC substrate. We have investigated the Al distribution in 4H-SiC through the variation of the implantation energies and the corresponding ratio of the doses. The implantation energies controlled 40, 60, 80, 100 and 120 keV and the implantation doses varied from $2\times10^{14}$ to $1\times10^{15}cm^{-2}$. In the simulation results, the Al ion distribution was deeper as increasing implantation energy and the doping level increased as increasing implantation doses. After the post-implantation annealing, the electrical properties of Al-implanted p-n junction diode were investigated by SILV ACO ATLAS numerical simulator.

• Journal of the Korean Magnetics Society
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• v.6 no.2
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• pp.93-97
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• 1996

The effects of annealing after deposition on the magnetic and magneto-optical properties of MnSbPt thin films prepared by rf sputtering were investigated. The MnSbPt alloy thin films were annealed in a vacuum with $10^{-5}$ Torr and the air, respectively, as a function of temperature and time. The films annealed at $300^{\circ}C$ for 4 hours was found to have the highest value of the saturation magnetization. The films annealed in the air did not show any thermal degradations, which indicates their chemical stability for the magneto-optical recording process. It was revealed that the $Mn_{43}Sb_{46}Pt_{11}$ films annealed at $300^{\circ}C$ for 4hours in a vacuum with $10^{-5}$ Torr exhibit high Kerr rotation angle of $0.8^{\circ}$ for the incident wavelength of 550nm, which is ascribed to the increase of the volume ratio of Clb phase. However, similar to the PtMnSb alloy thin films, these films are still horizontally magnetized and have the coercive field less than 400 Oe.

• Proceedings of the Optical Society of Korea Conference
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• 2006.07a
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• pp.197-198
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• 2006

본 연구에서 개발하는 성형렌즈는 그림1과 같이 한쪽 면이 비구면인 평볼록 형상이다. Glass렌즈의 고온압축성형을 위해서는 초정밀 가공기술로 제작된 성형Mold가 필요하며, Mold재질에 따른 성형기술의 확립이 필수적이다. 또한, 성형Mold의 표면과 융착반응이 없는 Glass소재가 요구된다. 본 실험을 위한 성형Mold는 코발트(Co) 함량 0.5 %의 초경합금(WC; 일본, Everloy社, 002K)을 초정밀 연삭가공하여 제작하였다. Glass소재는 전이점(Transformation Point; Tg) $572\;^{\circ}C$,항복점(Yielding Point; At) $630\;^{\circ}C$의 열적 특성을 갖는 K-BK7(일본, Sumita社)을 사용하였으며, d선에서 굴절률 및 아베수는 각각 1.51633, 64.1이다. 비구면 Glass렌즈 성형은 GMP(Glass Molding Press; 일본, Sumitomo社, Nano Press-S)장비를 사용하여 성형온도 $625\;^{\circ}C$, 서냉온도 $550\;^{\circ}C$로 고정하고 성형압력를 200-800 N 범위에서 변화시켰다. 표 1에 성형변수로 사용한 서냉속도와 서냉전환온도 조건을 나타낸다. 표1과 같이 각 서냉조건별로5장의 렌즈를 성형 후 특성값이 평균치에 가까운 3장을 선별하여 그 특성을 비교하였다. 각 조건에 따른 성형렌즈의 형상정도(일본, Panasonic社, UA3P, 자유곡면형상측정기), 두께(일본, Mitutoyo社, MDC-25M, 마이크로메터), 굴절률(일본, Shimatus社, KPR-200, 정밀굴절률측정기) 및 MTF[해상도](독일, Trioptics社, Image Master HR, MTF-Field)를 측정하여 각각의 광학적 특성을 비교 평가하였다. 비구면 Glass렌즈 성형장비와 형상측정기를 그림 2, 3에 각각 나타낸다.

• Journal of the Korean Ceramic Society
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• v.43 no.11 s.294
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• pp.688-692
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• 2006

Ferroelectric lanthanides-substituted $Bi_4Ti_3O_{12}$ $(Bi_{4-x}Ln_xTi_3O_{12}, BLnT)$ thin films approximately 200 nm in thickness were deposited by metal organic chemical vapor deposition onto Pt(111)/Ti/SiO$_2$/Si(100) substrates. Many researchers reported that the lanthanides substitution for Bi in the pseudo-perovskite layer caused the distortion of TiO$_6$ octahedron in the a-b plane accompanied with a shift of the octahedron along the a-axis. In this study, the effect of lanthanides (Ln=Pr, Eu, Gd, Dy)-substitution and crystallization temperature on their ferroelectric properties of bismuth titanate $(Bi_4Ti_3O_{12}, BIT)$ thin films were investigated. As BLnT thin films were substituted to lanthanide elements (Pr, Eu, Gd, Dy) with a smaller ionic radius, the remnant polarization (2P$_r$) values had a tendency to increase and made an exception of the Eu-substituted case because $Bi_{4-x}Eu_xTi_3O_{12}$ (BET) thin films had the smaller grain sizes than the others. In this study, we confirmed that better ferroelectric properties can be expected for films composed of larger grains in bismuth layered peroskite materials. The crystallinity of the thin films was improved and the average grain size increased as the crystallization temperature,increased from 600 to 720$^{\circ}C$. Moreover, the BLnT thin film capacitor is characterized by well-saturated polarization-electric field (P-E) curves with an increase in annealing temperature. The BLnT thin films exhibited no significant degradation of switching charge for at least up to $1.0\times10^{11}$ switching cycles at a frequency of 1 MHz. From these results, we can suggest that the BLnT thin films are the suitable dielectric materials for ferroelectric random access memory applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.377-385
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• 2018

For the investigation of dopant profiles in implanted $Si_{1-x}Ge_x$, the implanted B and As profiles are measured using SIMS (secondary ion mass spectrometry). The fundamental ion-solid interactions of implantation in $Si_{1-x}Ge_x$ are discussed and explained using SRIM, UT-marlowe, and T-dyn programs. The annealed simulation profiles are also analyzed and compared with experimental data. In comparison with the SIMS data, the boron simulation results show 8% deviations of $R_p$ and 1.8% deviations of ${\Delta}R_p$ owing to relatively small lattice strain and relaxation on the sample surface. In comparison with the SIMS data, the simulation results show 4.7% deviations of $R_p$ and 8.1% deviations of ${\Delta}R_p$ in the arsenic implanted $Si_{0.2}Ge_{0.8}$ layer and 8.5% deviations of $R_p$ and 38% deviations of ${\Delta}R_p$ in the $Si_{0.5}Ge_{0.5}$ layer. An analytical method for obtaining the dopant profile is proposed and also compared with experimental and simulation data herein. For the high-speed CMOSFET (complementary metal oxide semiconductor field effect transistor) and HBT (heterojunction bipolar transistor), the study of dopant profiles in the $Si_{1-x}Ge_x$ layer becomes more important for accurate device scaling and fabrication technologies.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.20-20
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• 2007

Nanowire-based field-effect transistors (FETs) decorated with nanoparticles have been greatly paid attention as nonvolatile memory devices of next generation due to their excellent transportation ability of charge carriers in the channel and outstanding capability of charge trapping in the floating gate. In this work, top-gate single ZnO nanowire-based FETs with and without Au nanoparticles were fabricated and their memory effects were characterized. Using thermal evaporation and rapid thermal annealing processes, Au nanoparticles were formed on an $Al_2O_3$ layer which was semi cylindrically coated on a single ZnO nanowire. The family of $I_{DS}-V_{GS}$ curves for the double sweep of the gate voltage at $V_{DS}$ = 1 V was obtained. The device decorated with nanoparticles shows giant hysterisis loops with ${\Delta}V_{th}$ = 2 V, indicating a significant charge storage effect. Note that the hysterisis loops are clockwise which result from the tunneling of the charge carriers from the nanowire into the nanoparticles. On the other hand, the device without nanoparticles shows a negligible countclockwise hysterisis loop which reveals that the influence of oxide trap charges or mobile ions is negligible. Therefore, the charge storage effect mainly comes from the nanoparticles decorated on the nanowire, which obviously demonstrates that the top-gate single ZnO nanowire-based FETs decorated with Au nanoparticles are the good candidate for the application in the nonvolatile memory devices of next generation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.207-210
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• 2005

In order to investigate the influence of the homo buffer layer on the microstructure of the ZnO thin film, undoped ZnO buffer layer were deposited on sapphire (0001) substrates by ultra high vaccum pulsed laser deposition (UHV-PLD) and molecular beam eiptaxy (MBE). After high temperature annealing at $600^{\circ}C$ for 30min, undoped ZnO buffer layer was deposited with various oxygen pressure (35~350mtorr). On the grown layer of undoped ZnO, Arsenic-doped(l, 3wt%) ZnO layers were deposited by UHV-PLD. The optical property of the ZnO was analyzed by the photoluminescence (PL) measurement. From $\Theta-2\Theta$ XRD analysis, all the films showed strong (0002) diffraction peak, and this indicates that the grains grew uniformly with the c-axis perpendicular to the substrate surface. Field emission scanning electron microscope (FE-SEM) revealed that microstructures of the ZnO were varied with oxygen pressure, arsenic doping level, and the deposition method of undoped ZnO buffer layers. The films became denser and smoother in the cases of introducing MBE-buffer layer and lower oxygen pressure during As-doped ZnO deposition. Higher As-doping concentration enhanced the columnar-character of the films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.169-170
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• 2006

In this study, ultra thin films of ferroelectric vinylidene fluoride-trifluoroethylene (VF2-TrFE) copolymer were fabricated on degenerated Si (n+, $0.002\;{\Omega}{\cdot}cm$) using by spin coating method. A 1~5 wt% diluted solution of purified vinylidene fluoride-trifluoroethylene (VF2:TrFE=70:30) in a dimethylformamide (DMF) solvent were prepared and deposited on silicon wafers at a spin rate of 2000~5000rpm for 30 seconds. After annealing in a vacuum ambient at $200^{\circ}C$ for 60 min, upper gold electrodes were deposited by vacuum evaporation for electrical measurement. X-ray diffraction results showed that the VF2-TrFE films on Si substrates had $\beta$-phase of copolymer structures. The capacitance on $n^+$-Si(100) wafer showed hysteresis behavior like a butterfly shape and this result indicates clearly that the dielectric films have ferroelectric properties. The typical measured remnant polarization (2Pr) and coercive filed (EC) values measured using a computer controlled a RT-66A standardized ferroelectric test system (Radiant Technologies) were about $0.54\;C/cm^2$ and 172 kV/cm, respectively, in an applied electric field of ${\pm}0.75\;MV/cm$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.473-479
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• 2011

In this paper, we have compared amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) with the nano-crystalline embedded-IGZO ($N_c$-embedded-IGZO) TFT fabricated by solid-phase crystallization (SPC) technique. The field effect mobility (${\mu}_{FE}$) of $N_c$-embedded-IGZO TFT was 2.37 $cm^2/Vs$ and the subthreshold slope (S-factor) was 0.83 V/decade, which showed lower performance than those of a-IGZO TFT (${\mu}_{FE}$ of a-IGZO was 9.67 $cm^2/Vs$ and S-factor was 0.19 V/decade). This results originated from generation of oxygen vacancies in oxide semiconductor and interface between gate insulator and semiconductor due to high temperature annealing process. However, the threshold voltage shift (${\Delta}V_{TH}$) of $N_c$-embedded-IGZO TFT was 0.5 V, which showed 1 V less shift than that of a-IGZO TFT under constant current stress during $10^5$ s. This was because there were additionally less increase of interface trap charges in Nc-embedded-IGZO TFT than a-IGZO TFT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.458-462
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• 2011

Soution-processed ZrInZnO (ZIZO) thin-film transistors (TFTs) with varying Zr content were fabricated. The ZIZO TFT (Zr=20 at. %/Zn) has an optimal performance with the saturation field effect mobility of 0.77 $cm^2/Vs$, the threshold voltage (Vth) of 2.1 V, the on/off ratio of $4.95{\times}10^6$, and subthreshold swing (S.S) of 0.73 V/decade. Using this optimized ZIZO TFT, the positive and negative gate bias stress according to annealing temperature was also investigated. While the Vth shifts dramatically after 1,000 s of both gate bias stresses, variations in the S.S are negligible. It suggests that electrons or holes are tem porarily trapped in the gate insulator, the semiconductor, or the interface between both layers.