Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Study on the Electrical Characteristics of Solution-processed ZrInZnO Thin-film Transistors

액상공정으로 제작된 ZrInZnO 박막 트랜지스터의 전기적 특성에 관한 연구

  • Jeong, Tae-Hoon (School of Electrical and Electronic Engineering, Yonsei University) ;
  • Kim, Si-Joon (School of Electrical and Electronic Engineering, Yonsei University) ;
  • Yoon, Doo-Hyun (School of Electrical and Electronic Engineering, Yonsei University) ;
  • Jeong, Woong-Hee (School of Electrical and Electronic Engineering, Yonsei University) ;
  • Kim, Dong-Lim (School of Electrical and Electronic Engineering, Yonsei University) ;
  • Lim, Hyun-Soo (School of Electrical and Electronic Engineering, Yonsei University) ;
  • Kim, Hyun-Jae (School of Electrical and Electronic Engineering, Yonsei University)
  • 정태훈 (연세대학교 전기전자공학과) ;
  • 김시준 (연세대학교 전기전자공학과) ;
  • 윤두현 (연세대학교 전기전자공학과) ;
  • 정웅희 (연세대학교 전기전자공학과) ;
  • 김동림 (연세대학교 전기전자공학과) ;
  • 임현수 (연세대학교 전기전자공학과) ;
  • 김현재 (연세대학교 전기전자공학과)
  • Received : 2011.05.03
  • Accepted : 2011.05.17
  • Published : 2011.06.01
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Abstract

Soution-processed ZrInZnO (ZIZO) thin-film transistors (TFTs) with varying Zr content were fabricated. The ZIZO TFT (Zr=20 at. %/Zn) has an optimal performance with the saturation field effect mobility of 0.77 $cm^2/Vs$, the threshold voltage (Vth) of 2.1 V, the on/off ratio of $4.95{\times}10^6$, and subthreshold swing (S.S) of 0.73 V/decade. Using this optimized ZIZO TFT, the positive and negative gate bias stress according to annealing temperature was also investigated. While the Vth shifts dramatically after 1,000 s of both gate bias stresses, variations in the S.S are negligible. It suggests that electrons or holes are tem porarily trapped in the gate insulator, the semiconductor, or the interface between both layers.

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References

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