• Journal of Information Display
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• 제4권1호
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• pp.1-8
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• 2003

Recent progress in both low pretilt and high pretilt defect free C1 surface stabilized ferroelectric liquid crystal (SSFLC) devices is reviewed. First, by numerical calculation to investigate the balance between surface azimuthal anchoring energy and bulk elastic energy within the confined chevron layer geometry of C1 and C2, it is possible to achieve a zigzag free C1 state by low azimuthal anchoring alignment with a low pretilt angle. The critical azimuthal anchoring coefficient for defect free C1 state is calculated. Its relationship with elastic constant, chevron angle as well as surface topography effect are also discussed. Second, using $5^{\circ}$ oblique SiO deposition alignment method a defect free, large memory angle, high contrast ratio and bistable C1 SSFLC display, which has potential for electronic paper applications has also been developed. The electrooptical properties and bistability of this device have been investigated. Various aspects of defect control are also discussed.

• 한국통신학회논문지
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• 제34권11A호
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• pp.904-908
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• 2009

The PZT(lead, zirconium, titanium) based ceramics which, are reported to be ferroelectric materials have their important applications in the areas of surface acoustic waves (SAW), filters, infrared detectors, actuators, ferroelectric random acess memory, speakers, electronic switches etc. Moreover, these PZT materials possess the large electromechanical coupling factor, large spontaneous polarization, low dielectric loss and low internal stress etc. Hence, keeping in view the unique properties of PZT piezoelectric ceramics we also tried to synthesize indigenously the small sized PZT ceramic powder in the laboratory by using the modified sol-gel approach. In this paper, Propyl alcohol based sol-gel method was used for preparation of PZT piezoelectric ceramic. The powder obtained by this sol-gel process was calcined and sintering to reach a pyrochlore-free crystal phase. The characterization of synthesized material was carried out by the XRD analysis and the surface morphology was determined by high resolution scanning electron microscopy.

• 한국세라믹학회지
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• 제44권5호
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• pp.141-143
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• 2007

Nanotubes and microtubes of ferroelectric lead zirconate titanate (PZT) were synthesized by means of a simple and convenient process called a template-wetting process. Nanoporous alumina and macroporous Si were used as template materials to fabricate the corresponding tubes. For the improvement of the wetting properties of the wetting solution, the PZT solution was mixed with a polymer. The polymer was removed completely during annealing. The grain growth processes of the PZT nanotubes during baking and furnace annealing were examined by means of field emission electron microscope (FE-SEM) and X-ray diffractometry (XRD).

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.69-72
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• 2002

B $i_{3.3}$L $a_{0.7}$ $Ti_3$ $O_{12}$(BLT) 강유전체 박막을 $Al_2$ $O_3$/Si 기판위에 졸-겔(sol-gel)법으로 스핀 코팅하여 Metal-Ferroelectric-Insulator-Silicon (MFIS) 구조를 형성하였다. 박막의 결정화를 위해 as-coated 박막을 산소분위기에서 $650^{\circ}C$ 및 $700^{\circ}C$에서 30분 동안 후속열처리를 실시하였다. BLT 박막의 열처리 온도를 $650^{\circ}C$에서 $700^{\circ}C$로 증가시킴에 따라서 c축으로 우선 배향되는 경향을 보였으며, FWHM 값이 감소하여 결정성이 향상됨을 확인할 수 있었다. $700^{\circ}C$에서 열처리된 BLT 박막의 memory window는 약 2.5V (인가전압 5V)를 나타내었으며, 누설전류는 약 1.5x$10^{-7}$ A/$\textrm{cm}^2$를 나타내었다.다.다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 추계학술대회 논문집
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• pp.48-51
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• 1997

(Pb. La)TiO$_3$ thin films were fabricated by sol-gel Processing and spin-coated on the Pt substrate. The spin-coated PLT films were sintered at 75$0^{\circ}C$ for 5min by rapid thermal ann La content dependence of the electrical properties of the PLT thin films are discussed. Wit La mole% from 20 to 36mo1e%. the dielectric constant of the PLT thin films decreased f 570. P-E hysteresis loops changed from ferroelectric to paraelectric. and the charge storage charging time decreased. The Curie Point decreased with increasing La content. The leak density also decreased and La 36mo1% species shows mood characteristics less than 10- electric field 500 (KV/cm) Because of the broad range of composition-controlled ferroelectric PLT thin films are suitable for memory application.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.439-444
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• 2005

We investigated the structural and electrical properties of BLT films grown on Si covered with $ZrO_{2}$ buffer layer. The BLT thin film and $ZrO_{2}$ buffer layer were fabricated using a metalorganic decomposition method. The electrical properties of the MFIS structure were investigated by varying thickness of the $ZrO_{2}$ layer. AES and TEM show no interdiffusion and reaction that suppressed using the $ZrO_{2}$ film as a buffer layer The width of the memory window in the C-V curves for the MFIS structure decreased with increasing thickness of the $ZrO_{2}$ layer. It is considered that the memory window width of MFIS is not affected by remanent polarization. Leakage current density decreased by about four orders of magnitude after using $ZrO_{2}$ buffer layer. The results show that the $ZrO_{2}$ buffer layers are prospective candidates for applications in MFIS-FET memory devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.172-173
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• 2006

Metal-ferroelectric-insulator-semiconductor (MFIS) structures with $Bi_{3.35}La_{0.75}Ti_3O_{12}$ (BLT) ferroelectric film and Zirconium oxide ($ZrO_2$) layer were fabricated on p-type Si(100). $ZrO_2$ and BLT films were prepared by sol-gel technique. Surface morphologies of $ZrO_2$ and BLT film were measured by atomic force microscope (AFM). The electrical characteristics of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si film were investigated by C-V and I-V measurements. No hysteretic characteristics was observed in the C-V curve of the Au/$ZrO_2$/Si structure. The memory window width m C-V curve of the Au/BLT/$ZrO_2$/Si diode was about 1.3 V for a voltage sweep of ${\pm}5$ V. The leakage current of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si structures were about $3{\times}10^{-8}$ A at 30 MV/cm and $3{\times}10^{-8}$ A at 3 MV/cm, respectively.

• 한국진공학회지
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• 제11권4호
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• pp.230-234
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• 2002

고온 급속 열처리를 행한 $LiNbO_3Si$/(100) 구조를 가지고 여러 가지 전극을 사용하여 금속/강유전체/반도체 커패시터를 제작하였으며, 제작한 커패시터의 비휘발성 메모리 응용 가능성을 확인하였다. MFS 커패시터의 C-V 특성 곡선에서는 LiNbO$_3$박막의 강유전성으로 인한 히스테리시스 특성이 관측되었으며, 1 MHz C-V 특성 곡선의 축적 영역에서 산출한 비유전율은 약 25 이었다. Pt 전극을 사용하여 제작한 커패시터에서는 인가 전계 500 kV/cm 범위에서 $1\times10^{-8}$ A/cm 이하의 우수한 누설전류 특성이 나타났다. midgap 부근에서의 계면 준위 밀도는 약 $10^{11}\textrm{cm}^2$.eV 이었으며, 잔류분극 값은 약 1.2 $\muC/\textrm{cm}^2$ 였다. Pt 전극과 A1 전극 모두 500 kHz 주파수의 바이폴러 펄스를 인가하면서 측정한 피로 특성에서 $10^{10}$ cycle 까지 측정된 잔류 분극 값이 초기 값과 같았다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.132-138
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• 2003

We investigated the polarization retention characteristics of ferroelectric capacitors with $Pb(Zr,Ti)O_3$ (PZT) thin films which were fabricated by different deposition methods. In thermally-accelerated retention tests, PZT films which were prepared by a chemical solution deposition (CSD) method showed rapid decay of retained polarization charges as the thickness of the films decreased down to 100 nm, while the films which were grown by metal organic chemical vapor deposition (MOCVD) retained relatively large non-volatile charges at the corresponding thickness. We concluded that in the CSD-grown films, the thicker interfacial passive layer compared with the MOCVD-grown films had an unfavorable effect on retention behavior. We observed the existence of such interfacial layers by extrapolation of the total capacitance with thickness of the films and the capacitance of these layers was larger in MOCVD-grown films than in CSD-grown films. Due to incomplete compensation of surface polarization charges by the free charges in the metal electrodes, the interfacial field activated the space charges inside the interfacial layers and deposited them at the boundary between the ferroelectric layer and the interfacial layer. Such space charges built up an internal field inside the films, which interfered with domain wall motion, so that retention property at last became degraded. We observed less imprint which was a result of less internal field in MOCVD-grown films while large imprint was observed in CSD-grown films.

• 한국세라믹학회지
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• 제32권12호
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• pp.1408-1416
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• 1995

Microstructure and ferroelectric properties of sol-gel derived PZT(52/48) and PT interlayered PZT(52/48) thin films on Pt/Ti/SiO2/Si substrates were investigated. Films were fabricated using Acetylacetone chelated PT and PZT(52/48) sols. PZT(52/48) thin films annealed at $700^{\circ}C$ for 20 min showed the rosette structure with the size of 1.2~1.6${\mu}{\textrm}{m}$ and the pyrochlore phse was contained. PT interlayered PZT thin films, which is inserted by PbTiO3 thin layer with the thickness of 130 $\AA$ between PZT thin film and electrode, consisted of a single perovskite phase after annealing above 55$0^{\circ}C$. They exhibited the uniform and columnar grains of 0.1~0.16${\mu}{\textrm}{m}$, which are applicable for microelectronic device including non-volatile memory. Typical P-E hysteresis loops could be obtained from PT interlayered PZT thin film at as low as the annealing temperature of 50$0^{\circ}C$. Ferroelectric properties of PT interlayered PZT thin films were improved as increasing annealing temperature up to $700^{\circ}C$, and then deteriorated at 75$0^{\circ}C$. PZT(52/48) and PT interlayered PZT(52/48) thin film annealed at $700^{\circ}C$ for 20 min displayed Ps=38.8$\mu$C/$\textrm{cm}^2$, Pr=10.0$\mu$C/$\textrm{cm}^2$, Ec=65.3 kV/cm and Ps=28.5$\mu$C/$\textrm{cm}^2$, Pr=9.8$\mu$C/$\textrm{cm}^2$, Ec=76.1 kV/cm, respectively.