• E2M - 전기 전자와 첨단 소재
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• 제10권4호
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• pp.349-354
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• 1997

This paper aims at studying the improvement of test method for t-weight sensitive fault (t-wsf) detect. The development of RAM fabrication technology results in not only the increase at device density on chips but also the decrease in line widths in VLSI. But, the chip size that was large and complex is shortened and simplified while the cost of chips remains at the present level, in many cases, even lowering. First of all, The testing patterns for RAM fault detect, which is apt to be complicated , need to be simplified. This new testing method made use of Local Lower Bound (L.L.B) which has the memory with the beginning pattern of 0(l) and the finishing pattern of 0(1). The proposed testing patterns can detect all of RAM faults which contain stuck-at faults, coupling faults. The number of operation is 6N at 1-weight sensitive fault, 9,5N at 2-weight sensitive fault, 7N at 3-weight sensitive fault, and 3N at 4-weight sensitive fault. This test techniques can reduce the number of test pattern in memory cells, saving much more time in test, This testing patterns can detect all static weight sensitive faults and pattern sensitive faults in RAM.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2004년도 춘계학술대회 논문집
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• pp.1274-1279
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• 2004

This paper proposes technique to detect ground fault in railway high voltage distribution lines. Overcurrent relay technique is widely used for detecting one line ground fault that occurs most frequently in railway high voltage distribution lines. However, ground fault in distribution line is usually high impedance fault with arc. Because the fault current magnitude measured in substation is very small, the conventional overcurrent relay can't detect the high impedance ground fault. Therefore this paper proposes the advanced technique using wavelet transform. It extracts D1 component from fault signals and detects fault comparing magnitude of D1 component in each phase. To evaluate this proposed technique, we model distribution system using PSCAD/EMTDC and extract various fault data. In conclusion this technique can detect ground fault including high impedance fault regardless of fault distance, fault impedance etc.

• 전기학회논문지
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• 제67권8호
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• pp.1113-1118
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• 2018

Protection in HVDC(High Voltage Direct Current) have the very fast velocity of fault detection. Because Fault in HVDC has the fast propagation, large currents, high interruption cost. The focus to velocity caused possibility of errors like a detection error like a high impedance fault. In this paper, Proposed complex composition for get the reliability and velocity. That used SFCL(Super Conducting Fault Current Limiter), Protection Zone and DTS(Distributed Temperature Sensing). The SFCL was detect the fault by quench and DTS&Protection Zone were perceive the detect by variation too. To examine the proposed method, PSCAD/EMTDC simulated. The results of simulation, proposed methods could the detect of fault to whole HVDC line. And that improved the reliability of fault clearing.

• 대한기계학회논문집B
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• 제41권11호
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• pp.735-742
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• 2017

본 연구에서는 PEM 연료전지 온도 센서의 고장을 감지 및 판별할 수 있는 모델 기반 센서 고장 감지 방법이 적용된다. 연료전지 차량이 작동하는 과정에서 스택 온도는 연료전지의 내구성에 영향을 미친다. 따라서 고장 진단 알고리즘이 고장 신호를 감지하는 것은 중요하다. 센서 고장 감지의 주요 목적은 연료전지 시스템의 안정적인 작동을 보장하여 고온과 저온으로부터 스택을 보호하는 것이다. 상태 공간에 기반한 패러티 방정식이 스택 온도와 냉각수 입구 온도와 같은 센서 고장을 감지하는데 적용되며, 잔차는 정상적인 온도 신호와 비교된다. 그리고 잔차는 현재의 센서 고장을 감지하는 다양한 고장 시나리오에 의해 평가된다. 결론적으로, 본 연구에서 설계된 고장 알고리즘이 고장 신호를 감지할 수 있다.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2000년도 춘계학술대회 논문집
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• pp.188-194
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• 2000

This study is about fault detection and fault area detection of LV circuit in Cab Cubicle system which have control of train to keep safety in High Speed Train. LV circuit is operated with diagnosis system like safety system. In this paper, we suggest a design and an implementation method to detect fault or to detect fault area automatically about LV circuit. The implemented system is tested successfully after implementation of some function. We expect reduction to diagnosis area or repair time by fault area module

• 항공우주기술
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• 제6권2호
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• pp.150-156
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• 2007

본 논문에서는 2축 자유도를 갖는 동조자이로 3개가 직교배치를 이루고 있는 관성항법 장치의 관성센서 고장검출기법에 대해 다루었다. 특히 동조자이로 고장특성을 고려하여 동조자이로 입력 축에 대한 고장 판단보다는 자이로 단위의 고장 판단을 수행하였으며, 보다 신뢰성 있는 고장 판단을 위해 검출할 고장 크기에 따른 개별 고장검출 모듈을 설정하였다. 큰 고장 감지는 현재 순간의 관성센서 정보만을 이용하는 방법을 이용하여 짧은 시간내에 고장판단이 가능하도록 하였으며, 작은 고장감지는 과거부터 현재까지 누적된 정보를 순차적으로 사용하여 고장판단에 소요되는 시간은 다소 길지만 보다 신뢰성 있는 고장정보를 제공하도록 하였다. 동조자이로 고장특성 및 고장 크기에 따른 개별 고장검출 모듈을 통해 성공적인 관성센서 고장검출이 가능함을 확인할 수 있었다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.55-55
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• 2000

This paper presents a fault detection and isolation(FDI) method based on Ceneralized Likelihood Ratio(GLR) test for the tightly coupled INS/GPS. State and measurement GLR tests detect INS or GPS fault. Once the fault is detected, Multi-hypothesized GLR scheme performs the fault isolation between INS and GPS and find which satellite malfunctions. Simulation results show that the GLR method is effective enough to detect and isolate a fault of the integrated navigation system.

• 한국통신학회논문지
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• 제22권7호
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• pp.1394-1402
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• 1997

In this work, an efficient test algorithm and BIST architeture a for embedded memories are presented. The proposed test algorithm can fully detect stuck-at fault, transition fault, coupling fault. Moreover, the proposed test algorithm can detect nighborhood pattern sensitive fault which could not be detected in previous march test algoarithms. The proposed test algorithm perposed test algorithm performs testing for neghborhood pattern sensitive fault using backgroung data which has been used word-oriented memory testing.

• 전자공학회논문지S
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• 제35S권1호
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• pp.68-79
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• 1998

In this paper, we propose a model-based FDI(fault detetion and isolation) algorithm to detect and isolate fault in a linear system. The proposed algorithm is gased on an HFC(hydrid fault classifier) which consists of an FCART2(fault classifier by ART2 neural network) and an FCFM(fault classifier by fault models) which operate in parallel to isolate faults. The proposed algorithm is functionally composed of three main parts-parameter estimation, fault detection, and isolation. When a change in the system occurs, the estimated parameters go through a transition zone in which errors between the system output and the stimated output and the estimated output cross a predetermined thrseshold, and in this zone the estimated parameters are tranferred to the FCART2 for fault isolation. On the other hand, once a fault in the system is detected, the FCFM statistically isolates the fault by using the error between ach fault model out put and the system output. From the computer simulation resutls, it is verified that the proposed model-based FDI algorithm can be performed successfully to detect and isolate faults in a position control system of a DC motor.

• 한국자동차공학회논문집
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• 제15권6호
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• pp.9-16
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• 2007

This paper describes the design and implementation of the fault diagnosis on the Electronic Throttle Control(ETC) System. The proposed fault diagnosis consists of an input signal, actuator and a processor diagnosis. The input signal diagnosis can detect the faults of the ETC system's input signals such as the position sensor fault, source voltage fault, load current fault, and desired position fault. The actuator diagnosis is able to detect the actuator fault due to the actuator aging and an obstacle which interfere in the movement of the actuator. The processor diagnosis detects the fault which prevents the microprocessor from operating the ETC software. In order to protect the breakdown of the ETC system and assure the driving safety, appropriate reactions are also proposed according to the detected faults. The safety and reliability of the ETC system can be improved by the proposed fault diagnosis.