• Progress in Superconductivity and Cryogenics
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• v.13 no.1
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• pp.17-21
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• 2011

A hybrid superconducting fault current limiter (SFCL) with fast switch had been previously suggested by our research group. To make a hybrid SFCL, different superconducting wires were wound two pancake coils so that two pancake coils had asymmetric configuration. The impedance of the asymmetric non-inductive coils are zero with applied normal current. However during the fault. currents were distributed unequally into the two pancake coils because each superconducting wires have different electrical characteristics. This unequal distribution of current causes effective magnetic flux which generate repulsive force. Fast switch was thus opened by the force applied to the aluminum plate which consists of SFCL. In this paper, the AC loss characteristics of the asymmetric non-inductive coils with combinations of superconducting wires were studied and calculated by related experiments and finite element method (FEM) simulation. From these results, we suggested the appropriate combination of two superconducting wires to be used for the asymmetric non-inductive coils.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.2
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• pp.160-166
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• 2015

This study proposes an improved cell balancing circuit for fast equalization among lithium-ion (Li-ion) batteries. A simple voltage sensorless charge balancing circuit has been proposed in the past. This cell balancing circuit automatically transfers energy from high-to low-voltage battery cells. However, the circuit requires a switch with low on-resistance because the balancing speed is limited by the on-resistance of the switch. Balancing speed decreases as the voltage difference among the battery cells decrease. In this study, the balancing speed of the cell balancing circuit is enhanced by using the auxiliary circuit, which boosts the balancing current. The charging current is determined by the nominal battery cell voltage and thus, the balancing speed is almost constant despite the very small voltage differences among the batteries. Simulation results are provided to verify the validity of the proposed cell balancing circuit.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.311-323
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• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.1188-1191
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• 2003

In this paper, we focus our attention on the improvement of locking time and jitter parameter and propose the new structure of PLL which combined with the FVC, FOVI Matcher(FVC-Output and VCO-input Matching Circuit), Control Circuit and the conventional charge pump PLL. Using fast operation characteristics of the FVC, the circuit matching FVC-Output and VCO-input (FOVI Matcher) made to synchronize very fast. Fast locking time is usually required for application where the PLL has to settle rapidly if they switch from an idle mode to a normal mode and to track high-frequency data bit rate in data recovery systems. After a fast acqusition is achieved by the using the FVC, the conventional PLL operates for removing the phase error between the reference signal and the feedback signal. Therefore this structure can improve the trade-off between acquisition behavior and locked behavior.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1791-1804
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• 2018

To achieve a fast dynamic response and to solve the multi-objective control problems of the output currents, capacitor voltages and system constraints, this paper proposes a deadbeat and hierarchical predictive control with space-vector modulation (DB-HPC-SVM) for five-level nested neutral point piloted (NNPP) converters. First, deadbeat control (DBC) is adopted to track the reference currents by calculating the deadbeat reference voltage vector (DB-RVV). After that, all of the candidate switching sequences that synthesize the DB-RVV are obtained by using the fast SVM principle. Furthermore, according to the redundancies of the switch combination and switching sequence, a hierarchical model predictive control (MPC) is presented to select the optimal switch combination (OSC) and optimal switching sequence (OSS). The proposed DB-HPC-SVM maintains the advantages of DBC and SVM, such as fast dynamic response, zero steady-state error and fixed switching frequency, and combines the characteristics of MPC, such as multi-objective control and simple inclusion of constraints. Finally, comparative simulation and experimental results of a five-level NNPP converter verify the correctness of the proposed DB-HPC-SVM.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.11
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• pp.456-463
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• 1984

The fast-rising high-voltage pulse generation circuit system of a theta pinch is both theoretically and experimentally investigated. The idealized model of this circuit system is a hybrid circuit system composed of three parts: a lumped circuit part being consisted of a capacitor bank and a spark switch connected in series, another lumped circuit part being consisted of the Blumlein transmission line, whose end load is the pinch coil. the voltage difference between two ends of the pinch coil is formulated by analyzing this hybrid circuit system by means of the law of the signal propagation in the transmission line and Kirchhoff's laws. The expedient numerical method for computer calculation is developed to generate the pulse profile of the voltage difference across the pinch coil. The period of the experimentally measured main pulse is a fourth of the theoretical one neglecting the resistance of the pinch coil. We attribute this discrepancy to the modelling in the theoretical calculation that hte resistance and inductance of the spark switch and capacitor bank are assumed to be constant through discharge. Therefore, we can see that the rise time of the imploding magnetic-field pulse is mainly dependent on the spark switch and capacitor bank.

• Progress in Superconductivity and Cryogenics
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• v.14 no.3
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• pp.53-59
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• 2012

Adiabatic demagnetization refrigerator (ADR) for hydrogen re-liquefaction operating between 24 K and 20 K has been designed. $Dy_{0.9}Gd_{0.1}Ni_2$, whose Curie temperature is 24 K, is selected as a magnetic refrigerant. The magnetic refrigerant powder is sintered with oxygen-free high purity copper (OFHC) powder to enhance its effective thermal conductivity as well as to achieve relatively high frequency. A perforated plate heat exchanger (PPHE) operated with forced convection is utilized as a heat switch. The forced convection heat switch is expected to have fast response relative to a conventional gas-gap heat switch. A conduction-cooled high Tc superconducting (HTS) magnet is employed to apply external magnetic field variation on a magnetic refrigerant. $2^{nd}$ generation GdBCO coated conductor HTS tape with Kapton$^{(R)}$ insulation (SUNAM Inc.) will be utilized for the HTS magnet. The magnetization and demagnetization processes are to be achieved by the AC operation of the HTS magnet. The designed magnetic field and target ramp rate of the HTS magnet are over 4 T with 180 A and 0.4 T/s, respectively. AC loss distribution on HTS magnet is theoretically estimated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.937-944
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• 2002

The current fast-growing Internet traffic is demanding more and more network capacity. Photonic packet switching offers high-speed, data rate/format transparency, and configurability, which are some of the important characteristics needed in future networks supporting different forms of data. In this paper, we define that optical backbone networks for IP transport consist of optical packet core switches and optical fibers. We propose a multi-link photonic packet switch managing as single media which unifies the whole bandwidth of multiple wavelengths on the optical fiber in the WDM optical networks. The proposed switch uses optical packet memories of output link equally as well as using the WDM buffer. So it cuts down the required number of buffers and realizes of the optical packet memory economically.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.1
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• pp.74-80
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• 2007

This paper proposes the novel open-fault detection/isolation scheme of inverter switch in two-phase excited VSI. This scheme identify open-fault using voltage sensor at lower switches of each phase according to the operating mode. It has benefit of simple implementation, fast detection and robustness in the load so that stab of the system is improved. Also, at faulty mode, it minimizes faulty effect and makes possible continuous operation through the reconfiguration procedure applying four-switch operation. The validity of proposed fault detection scheme is verified by experimental results.

• Journal of Power Electronics
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• v.17 no.3
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• pp.798-810
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• 2017

This paper presents a combined system of a small-capacity inverter and multigroup delta-connected thyristor switched capacitors (TSCs). The system is referred to as a hybrid static compensator (HSC) and has the functions of dynamic reactive power compensation and harmonic suppression. In the proposed topology, the load reactive power is mainly compensated by the TSCs. Meanwhile the inverter is meant to cooperate with TSCs to achieve continuous reactive power compensation, and to filter the harmonics generated by nonlinear loads and the TSCs. First, the structure and mathematical model of the HSC are discussed Then the control method of the HSC is presented. An improved reduced order generalized integrator (ROGI)-based selective current control method is adopted in the inverter to achieve high-performance reactive and harmonic current compensation. Meanwhile, a switch control strategy is proposed to implement precise and fast switching of the TSCs and to avoid changing the time delay needed by the conventional switch strategy. Experiments are implemented on a 20 KVA HSC prototype and the obtained results verify the validity of the proposed HSC system.