• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.2
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• pp.88-95
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• 2008

This paper proposes a fast fault detection algorithm under open-circuit fault of a switch for a brushless DC(BLDC) motor drive system. This proposed method is configured without the additional devices for fault detection and identification. The fault detection and identification are achieved by a simple algorithm using the operating characteristic of the BLDC motor. After the fault identification, the drive system is reconfigured for continuous operation. This system is reconfigured by four-switch topology connecting a faulty leg to the middle point of DC-link bidirectional switches. This proposed method can also be embedded into existing BLDC motor drive systems as a subroutine without excessive computational effort. The feasibility of a the proposed fault detection algorithm is validated in simulation and experiment.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.54 no.8
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• pp.375-387
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• 2005

This paper presents an application of parallel Genetic Algorithm-Tabu Search (GA-TS) algorithm to search an optimal solution of a service restoration in distribution systems. The main objective of service restoration of distribution systems is, when a fault or overload occurs, to restore as much load as possible by transferring the do-energized load in the out of service area via network reconfiguration to the appropriate adjacent feeders at minimum operational cost without violating operating constraints, which is a combinatorial optimization problem. This problem has many constraints with many local minima to solve the optimal switch position. This paper develops parallel GA-TS algorithm for service restoration of distribution systems. In parallel GA-TS, GA operators are executed for each processor. To prevent solutions of low fitness from appearing in the next generation, strings below the average fitness are saved in the tabu list. If best fitness of the GA is not changed for several generations, TS operators are executed for the upper $10\%$ of the population to enhance the local searching capabilities. With migration operation, best string of each node is transferred to the neighboring node after predetermined iterations are executed. For parallel computing, we developed a PC cluster system consists of 8 PCs. Each PC employs the 2 GHz Pentium IV CPU and is connected with others through ethernet switch based fast ethernet. To show the validity of the proposed method, proposed algorithm has been tested with a practical distribution system in Korea. From the simulation results, we can find that the proposed algorithm is efficient for the distribution system service restoration in terms of the solution quality, speedup, efficiency and computation time.

• Progress in Superconductivity
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• v.10 no.1
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• pp.60-67
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• 2008

We present domestic efforts for superconducting fault current limiter (SFCL) application in the Korea Electric Power Corporation (KEPCO) grid and pending points at issue. KEPCO's decision to upgrade the 154 kV/22.9 kV main transformer from 60 MVA to 100 MVA cast a problem of high fault current in the 22.9 kV distribution lines. The grid planners supported adopting an SFCL to control the fault current. This environment friendly to SFCL application must be highly dependent upon the successful development of SFCL having specifications that domestic utility required. The required conditions are (1) small size of not greater than twice of 22.9 kV gas insulated switch-gear (GIS), (2) sustainability of current limitation without the line breaking by circuit breakers (CB) for maximum 1.5 seconds. Also, optionally, recommended is (3) the reclosing capability. Conventional resistive SFCLs do not meet (1) $\sim$ (3) all together. A hybrid SFCL is an excellent solution to meet the conditions. The hybrid SFCL consists of HTS SFCL components for fault detection and line commutation, a fast switch (FS) to break the primary path, and a limiter. This characteristic structure not only enables excellent current limiting performances and the reclosing capability, but also allows drastic reduction of HTS volume and small size of the cryostat, resulting in economic feasibility and compactness of the equipment. External current limiter also enables long term limitation since it is far less sensitive to heat generation than HTS. Semi-active operation is another advantage of the hybrid structure. We will discuss more pending points at issues such as maintenance-free long term operation, small size to accommodate the in-house substation, passive and active control, back-up plans, diagnosis, and so on.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.5
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• pp.485-495
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• 2000

The parallel computer system that uses parallel program on the application such as a large scale business or complex operation is required. One of crucial operation of parallel computer system is synchronization. A representative method of synchronization is barrier synchronization. A barrier forces all process to wait until all the process reach the barrier and then releases all of the processes. There are software schemes, hardware scheme, or combinations of these mechanism to achieve barrier synchronization which tends to use hardware scheme. Besides, barrier synchronization lets parallel computer system fast because it has fewer start-up overhead. In this paper, we propose a new switch module that can implement fast and fault-tolerant barrier synchronization in hardware scheme. A proposed barrier synchronization is operated not in full-switch-driven method but in processor-driven method. An effective barrier synchronization is executed with inexpensive hardware supports. Therefore, a new proposed hardware barrier synchronization is designed that it is operated in arbitrary network topology. In this paper, we only show comparison of barrier synchronization on Multistage Interconnection Network. This research results in 24.6-24.8% reduced average delay. Through this result, we can expect lower average delay in irregular network.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.567-574
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• 2015

In this paper, a 50ns 256-kb EEPROM IP for MCU (micro controller unit) ICs is designed. The speed of data sensing is increased in the read mode by using a proposed DB sensing circuit of differential amplifier type which uses the reference voltage, and the switching speed is also increased by reducing the total DB parasitic capacitance as a distributed DB structure is separated into eight. Also, the access time is reduced reducing a precharging time of BL in the read mode removing a 5V NMOS transistor in the conventional RD switch, and the reliability of output data can be secured by obtaining the differential voltage (${\Delta}V$) between the DB and the reference voltages as 0.2*VDD. The access time of the designed 256-kb EEPROM IP is 45.8ns and the layout size is $1571.625{\mu}m{\times}798.540{\mu}m$ based on MagnaChip's $0.18{\mu}m$ EEPROM process.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.5
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• pp.400-409
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• 2001

A new phase-shifted parallel-input/series-output(PISO) dual converter for tush-power step-up applications has been proposed. Since the proposed converter shows a low switch turn-off voltage stress, switching devices with low conduction loss can be employed in order to improve the power conversion efficiency. Moreover, it features a low output capacitor root-mean-square(RMS) current stress, low input current and output voltage ripple contents, and fast control-to-output dynamics compared to its PWM counterpart. In this paper, the operation of the proposed converter is analyzed in detail and its mathematical models and steady-state solutions are presented. A comparative analysis with the conventional PWM PISO dual converter is also provided. To confirm the operation, features, and validity of the Proposed converter, experimental results from an 800W, 24-350Vdc prototype are presented.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.2
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• pp.115-122
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• 2007

In this paper, a novel fault detection method for fault tolerant control is proposed when the NPC inverter has a open failure in the switching device. The open fault of switching device is detected by checking the variation of a leg-voltage in the neutral-point-clamped inverter and the two phases control method is used for continuously balance the three phases voltage to the load. It can be achieve the fault tolerant control for improving the reliability of the NPC inverter by the fault detection and reconfiguration. This method has fast detection ability and a simple realization for fault detection, compared with a conventional method. Also, this fast detection ability improved the harmful effects such as DC-link voltage unbalance and overstress to other switching devices from a delay of fault detection. The proposed method has been verified by simulation and experiment.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1535-1544
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• 2017

Advances in FPGA technology have enabled fast real-time simulation of power converters, filters and loads. FPGA based HIL (Hardware-In-the-Loop) simulators have revolutionized control hardware and software development for power electronics. Common time step sizes in the order of 100ns are sufficient for simulating switching frequency current and voltage ripples. In order to keep the time step as small as possible, ideal switching function models are often used to simulate the phase legs. This often produces inferior results when simulating the discontinuous conduction mode (DCM) and disabled operational states. Therefore, the corresponding measurement and protection units cannot be tested properly. This paper describes a new solution for this problem utilizing a discrete-time PI controller. The PI controller simulates the proper DC and low frequency AC components of the phase leg voltage during disabled operation. It also retains the advantage of fast real-time execution of switch-based models when an accurate simulation of high frequency junction capacitor oscillations is not necessary.

• Journal of Digital Contents Society
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• v.18 no.6
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• pp.1193-1198
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• 2017

The IGBT structure developed in this paper is used as a high power switch semiconductor for DC transmission and distribution and it is expected that it will be used as an important electronic device for new and long distance DC transmission in the future by securing fast switching speed and improved breakdown voltage characteristic. As a new type of next generation power semiconductors, it is designed to improve the switching speed while at the same time improving the breakdown voltage characteristics, reducing power loss characteristics, and achieving high current density advantages at the same time. These improved properties were obtained by further introducing SiO2 into the N-drift region of the Planar IGBT and were compared and analyzed using the Sentaurus TCAD simulation tool.

• Journal of Sensor Science and Technology
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• v.23 no.4
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• pp.272-277
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• 2014

At present, the index of chemical oxygen demand (COD) is widely used as an indicator of organic water pollution with biochemical oxygen demand (BOD). But, traditional COD measurement method are not only with various chemical reagents exhausted, but also long time consumed, the operation procedure and the modification are much professional. This paper reported a novel COD measurement system using double-beam and multiple wavelength analysis UV-VIS spectrometries. It consists of pulsed xenon lamp, two-way optical fiber, optical switch, spectrometer and main processor. Proposed COD measurement system obtains any spectral information of water sample (KHP standard sample and two river water and wastewater) and reference sample (distilled water) in the range of 200~520 nm, corresponding to the COD concentration from 0 to 300 mg/L through calculating the UV absorbance. The system show improved precision and can work continuously fast at time interval about 25 seconds.