• Computational Structural Engineering
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• v.3 no.1
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• pp.97-107
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• 1990

The development of an improved degenerated shell element is presented in this paper. In the formulation of this element, an enhanced interpolation of transverse shear strains in the natural coordinate system is used to overcome the shear locking problem ; the reduced integration technique in in-plane strains is applied to avoid the membrane locking behavior ; and selective addition of the nonconforming displacement modes improve the element performances. This element is free of serious locking problems and undesirable compatible or commutable spurious kinematic deformation modes, and passes the patch tests. To illustrate the performance of this improved degenerated shell element, some benchmark problems are presented. Numerical results indicate that the new element shows fast convergence and reliable solutions.

• Journal of information and communication convergence engineering
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• v.3 no.3
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• pp.142-145
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• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• Structural Engineering and Mechanics
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• v.11 no.2
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• pp.123-132
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• 2001

An improved version of the Element-free Galerkin method (EFGM) is presented here for addressing the problem of transverse shear locking in shear-deformable beams with a high length over thickness ratio. Based upon Timoshenko's theory of thick beams, it has been recognized that shear locking will be completely eliminated if the rotation field is constructed to match the field of slope, given by the first derivative of displacement. This criterion is applied directly to the most commonly implemented version of EFGM. However in the numerical process to integrate strain energy, the second derivative of the standard Moving Least Square (MLS) shape functions must be evaluated, thus requiring at least a $C^1$ continuity of MLS shape functions instead of $C^0$ continuity in the conventional EFGM. Yet this hindrance is overcome effortlessly by only using at least a $C^1$ weight function. One-dimensional quartic spline weight function with $C^2$ continuity is therefore adopted for this purpose. Various numerical results in this work indicate that the modified version of the EFGM does not exhibit transverse shear locking, reduces stress oscillations, produces fast convergence, and provides a surprisingly high degree of accuracy even with coarse domain discretizations.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.2
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• pp.144-149
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• 2004

Register Controlled DLL with fast locking and low-power consumption, is described in this paper. Delay monitor scheme is proposed to achieve the fast locking and inverter is inserted in front of delay line to reduce the power consumption, also. Proposed DLL was fabricated in a 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS technology. The proposed delay monitor scheme enables the DLL to lock to the external clock within 4 cycles. The power consumption is 36㎽ with 3V supply voltage at 34MHz clock frequency.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3097-3099
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• 2000

In this paper, we design PLL for a low jitter and fast locking time that is used a new simple precharged CMOS phase frequency detector(PFD). The proposed PFD has a simple structure with using only 18 transistors. Futhermore, the PFD has a dead zone 25ps in the phase characteristic which is important in low jitter applications. The phase and frequency error detection range is not limited as the case of other precharge type PFDs. the simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD. the PLL using the new PED is designed using 0.25${\mu}m$ CMOS technology with 2.5V supply voltage.

• Journal of Information Technology Applications and Management
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• v.12 no.4
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• pp.59-70
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• 2005

Flash memories are one of best media to support portable computer's storages in mobile computing environment. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However, we need to improve traditional transaction management scheme due to the relatively slow characteristics of flash operation as compared to RAM memory. in order to achieve this goal, we devise a new scheme called Flash Two Phase Locking (F2PL) scheme for efficient transaction processing. F2Pl improves transaction performance by allowing multi version reads and efficiently handling slow flash write/erase operation in lock management process. We also propose a simulation model to show the performance of F2PL. Based on the results of the performance evaluation, we conclude that F2PL scheme outperforms the traditional scheme.

• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2378-2384
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• 2009

A novel phase-locked loop(PLL) architecture of sub-micron locking time has been proposed. Input frequency is multiplied by using a delay-locked loop(DLL). The input frequency of a PLL is multiplied while the PLL is out of lock. The multiplied input frequency makes the PLL having a wider loop bandwidth. It has been simulated with a $0.18{\mu}m$ 1.8V CMOS process. The simulated locking time is $0.9{\mu}s$ at 162.5MHz and 2.6GHz, input and output frequency, respectively.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1201-1204
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• 2003

This paper described a replica-delay adaptive lock-acquisition scheme for high-speed DLLs. The proposed scheme provides the fast and correct locking cycle that is variable according to the magnitude of the arbitrary replica delay (fixed delay). The scheme guarantees the wide operation range and the fast lock-aquisition time. It has been confirmed by HSPICE simulations in a 0.35${\mu}{\textrm}{m}$ CMOS process.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.13 no.4
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• pp.449-459
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• 2000

The original Mindlin-type degenerated shell element perform reasonably well for moderately thick shell structures. However, when full integration for analysis of thin shell is used to evaluate the stiffness matrix, the stiffness of shell element is often over-estimated due to shear or membrane locking phenomena. To correct this problem, the formulation of the new degenerated shell element is derived by the combination of two different techniques. The first type of elements(TypeⅠ) has used assumed shear strains in the natural coordinate system to overcome the shear locking problem, the reduced integration technique in in-plane strains(membrane strains) to avoid membrane locking behaviour. Another element(TypeⅡ) has applied the assumed strains to both of membrane strain and transverse shear strains. The improved degenerated shell element has been tested by several numerical problems of shell structures. Numerical results indicate that this shell element shows fast convergence and reliable solutions.