References
- K. Kurita, T. Hotta, and N. Kitamura, 'PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor', IEEE J. Solid State Circuits, vol. 26, pp. 585-589, APR. 1991 https://doi.org/10.1109/4.75059
- I. W. Young, J. K. Greason, and K. L. Wong, 'A PLL clock generator with 5 to 110MHz of lock range for microprocessor's, IEEE J. Solid State Circuits, vol. 34, pp.1599-1607, NOV. 1992
- J. Alvarez, H. Sanchez, G. Gerosa, and R. Countryman, 'A wide band width low voltage PLL for power PC microprocessors', IEEE J. Solid State Circuits, vol. 30, pp. 383-391, APR. 1995 https://doi.org/10.1109/4.375957
- V. R. von Kaenel, 'A high speed, low power clock generator for a microprocessor application', IEEE J. Solid State Circuits, vol. 33, pp. 1634-1639, NOV. 1998 https://doi.org/10.1109/4.726549
- George Chien, Paul R. Gray, 'A 900-MHz local oscillator using a DLL _based frequency multiplier technique for PCS applications', IEEE J. Solid State Circuits, vol. 35, pp. 1996-1999, DEC. 2000 https://doi.org/10.1109/4.890315
- David J. Foley, Michael P. Flynn, 'CMOS DLL_based 2V 3.2ps jitter 1GHz clock synthesizer and temperature compensated tunable oscillator', IEEE J. Solid State Circuits, vol. 36, pp. 417-423, MARCH 2001 https://doi.org/10.1109/4.910480
-
Chulwoo Kim, In-Chul Hwang, and Sung-Mo Kang, 'A low power small area
$\pm$ 7.23ps jitter 1GHz DLL_based clock generator ', IEEE J. Solid State Circuits, vol.37, pp.1414-1420, NOV. 2002 https://doi.org/10.1109/JSSC.2002.803936 - Guang-Kaai Edhng, Jyh-Woei Lin, Shen-Iuan Liu, 'A Fast-Lock Mixed-Mode DLL Using a 2-b SAR Algorithm', IEEE J. Solid State Circuits, vol. 36, pp. 1464-1471, OCT. 2001 https://doi.org/10.1109/4.953474