Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
권호 표지
DOI QR코드

DOI QR Code

Register Controlled Delay-locked Loop using Delay Monitor Scheme

Delay Monitor Scheme을 사용한 Register Controlled Delay-locked Loop

  • Published : 2004.02.01
Download PDF
⟨ Previous Next ⟩

Abstract

Register Controlled DLL with fast locking and low-power consumption, is described in this paper. Delay monitor scheme is proposed to achieve the fast locking and inverter is inserted in front of delay line to reduce the power consumption, also. Proposed DLL was fabricated in a 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS technology. The proposed delay monitor scheme enables the DLL to lock to the external clock within 4 cycles. The power consumption is 36㎽ with 3V supply voltage at 34MHz clock frequency.

Keywords

References

  1. Symposium on VLSI Circuit Digest of Technical Papers A Portable Digital DLL Architecture for CMOS Interface Circuit Bruno W. Garlepp;Kevin S. Donnelly;Jun Kim;Pak S. Chau;Jared L. Zerbe;Charles Huang; Chanh V. Tran;Clemez L. Pormann;Donald Stark;Yiu-Fai Chan;ThomasH. Lee;Mark A.;Horowitz
  2. J. of KIEEME v.11 no.6 A study on sol-like-bulk CMOS structure operationg in low voltage with stability S.H.Son;T.Jin
  3. 전기전자재료학회논문지 v.16 no.7 6H-SiC MOSFET과 디지털 IC제작 오충완;최재승;송지현;이장희;이형규;박근형;김영석 https://doi.org/10.4313/JKEM.2003.16.7.584
  4. 전기전자재료학회논문지 v.13 no.11 플래시메로리를 위한 Scaled SONOSFET NVSM의 프로그래밍 조건과 특성에 관한 연구 박희정;박승진;남동우;김병철;서광열
  5. IEEE J. Sold-State Circuit v.31 A 2.5-ns clock access, 250MHz, 256Mb SDRAM with synchronous mirror delay T.Saeki;Y.Nakaoka;M.Fujita;A.Tanaka;K.Nagata;K.Sakakibara;T.Matano;Y.Hoshino;K.Miyano;S.Isa;S.Nakazawa;E.Kakchashi;John Mark Drynan;M.Komuro;T.Fukase;H.Iwasaki;M.Takenaka;J.Sekine;M.Igeta;N.Nakanishi;T.Itani;K.Yoshida;H.Yoshino;S.Hashimoto;T.Yoshii;M.Ichinose;T.Imura;M.Uziie;S.Kikuchi;K.Koyama;Y.Fukuzo;T.Okuda https://doi.org/10.1109/JSSC.1996.542310
  6. IEICE Trans. Electron. v.E79-C no.6 Digital delay locked loop and design technique for high-speed synchronous interface Yoshinori Okajima;Masao Taguchi;Miki Yanagawa;Koichi Nishimura;Osamu Hamada
  7. ISSCC Digest of Technical Paper Partial Response Detection Technique for Driver Power Reduction in High-speed Memory - to - Processor Communications Hirotaka Tamura;Miyoshi Saito;Kohtaroh Gotoh;Shigetoshi Wakayama;Junji Ogawa;Yoshiharu Kato;Masao Taguchi;Takeshi Imamura
  8. Symposium on VLSI Circuit Digest of Technical Paper All-digital multiphase delay locked loop for internal timing generation in embedded and/or high-speed DRAMs Kohtaroh Gotoh;Shigetoshi Wakayama;Miyoshi Saito;Junji Ogawa;Hirotaka Tamura;Yoshinori Okajima;Masao Taguchi