• Journal of information and communication convergence engineering
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• v.9 no.3
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• pp.305-309
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• 2011

This paper proposes a new rotational frequency detector (RFD) for phase-locked loop (PLL) or clock and data recovery (CDR) applications for fast frequency acquisition. The proposed RFD uses the four states finite state machine (FSM) model to accelerate the frequency acquisition time. It is modeled and simulated with MATLAB Simulink. The functionalities of the proposed RFD are examined and the results are compared to those of a conventional RFD. The proposed RFD's frequency acquisition time is four times faster than that of a conventional one. The proposed RFD incorporated with a phase detector (PD) in PLL or CDR is expected to improve the frequency and phase acquisition performance later greatly.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.718-720
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• 1999

This paper describes a charge pump PLL architecture which achieves high frequency operation and fast acquisition. This architecture employs multi-phase frequency detector comprised of precharge type phase frequency detector and conventional phase frequency detector. Operation frequency is increased by using precharge type phase frequency detector when the phase difference is small and acquisition time is shortened by using conventional phase frequency detector and increased charge pump current when the phase difference is large. By virtue of this multi-phase frequency detector structure, the maximum operating frequency of 694MHz at 3.0V and faster acquisition were achieved by simulation.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.85-88
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• 2000

This paper describes a Band-Selective Charge-Pump PLL(CPPLL) for clock recovery and clock generator. The proposed PLL satisfies fast acquisition time and low jitter characteristics simultaneously by reducing initial frequency error. The acquisition time of the designed Band-Selective CPPLL can be decreased down to 55% of a conventional CPPLL.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.10
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• pp.479-485
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• 2001

In this paper, we introduce a charge pump phase-locked loop (PLL) architecture which employs a precharge phase frequency detector (PFD) and a sequential PFD to achieve a high frequency operation and a fast acquisition. Operation frequency is increased by using the precharge PFD when the phase difference is within $-{\pi}{\sim}{\pi}$ and acquisition time is shortened by using the sequential PFD and the increased charge pump current when the phase difference is larger than ${\pm}{\pi}$. So error detection range of the proposed PLL structure is not limited to $-{\pi}{\sim}{\pi}$ and a high frequency operation and a higher speed lock-up time can be achieved. The proposed PLL was designed using 1.5 ${\mu}m$ CMOS technology with 5V supply voltage to verify the lock in process. The proposed PLL shows successful acquisition for 200 MHz input frequency. On the other hand, the conventional PLL with the sequential PFD cannot operate at up to 160MHz. Moreover, the lock-up time is drastically reduced from 7.0 ${\mu}s\;to\;2.0\;{\mu}s$ only if the loop bandwidth to input frequency ratio is regulated by the divide-by-4 counter during the acquisition process. By virtue of this dual PFDs, the proposed PLL structure can improve the trade-off between acquisition behavior and locked behavior.

• ETRI Journal
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• v.32 no.1
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• pp.142-144
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• 2010

In this letter, we propose GPS L5 acquisition schemes to detect a fast code phase and improve the accuracy of the Doppler frequency. The proposed approach is based on the code-phase changes which occur during the acquisition processing time originating in the Doppler frequency. The proposed schemes detect a fast code phase within about 1 chip near the estimated code phase and improve the accuracy of the Doppler frequency by up to about 4 times in comparison with the popular Septentrio receiver. The feasibility of the proposed schemes is demonstrated through simulation.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.963-966
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• 2003

This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process.

• Journal of Positioning, Navigation, and Timing
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• v.4 no.4
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• pp.151-160
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• 2015

GPS L2C signal is a recently added civil signal to L2 frequency and is constructed by time division multiplexing of civil moderate (L2-CM) and civil long (L2-CL) code signals. While the L2-CM code is 20 ms-periodic and modulates satellite navigation message, the L2-CL code is 1.5s-periodic with 767,250 chips long code sequence and carries no data. Therefore, the L2-CL code signal allows receivers to perform a very long coherent integration. However, due to the length of the L2-CL code, the acquisition of the L2-CL code signal may take too long or require too much hardware resources. In this paper, we propose a three-step ultra-fast L2-CL code acquisition (TSCLA) technique for dual band GPS receivers. In the proposed TSCLA technique, a dual band GPS receiver sequentially acquires the coarse/acquisition (C/A) code signal at L1 frequency, the L2-CM code signal, and the L2-CL code signal to minimize mean acquisition time (MAT). The theoretical performance analysis and numerous Monte Carlo simulations show the significant advantage of the proposed TSCLA technique over conventional techniques introduced in the literature.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.6
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• pp.603-607
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• 2008

This paper proposes a fast acquisition method using INS velocity and multiple correlators for high speed vehicles. In order to reduce acquisition time in GPS receiver, the method utilizes inertial velocity information and multiple correlators. Search range of the Doppler frequency is reduced by using INS velocity and the number of cells at one search can be increased by using multiple correlators. By using both multiple correlators and the INS velocity in the acquisition, search space can be greatly reduced. Experimental results show that the method gives faster signal acquisition performance than the conventional method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.271-274
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• 2001

In this paper, we propose a charge pump phase-locked loop (PLL) with multi-PFD which is composed of a sequential phase frequency detector(PFD) and a precharge PFD. When the Phase difference is within - $\pi$ ∼ $\pi$ , operation frequency can be increased by using precharge PFD. When the phase difference is larger than │ $\pi$ │, acquisition time can be shorten by the additional control circuit with increased charge pump current. Therefore a high frequency operation, a fast acquisition and an unlimited error detection range can be achieved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6A
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• pp.685-692
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• 2008

In this paper, we propose a timing recovery loop for Inmarsat mini-m system downlink receiver. Inmarsat mini-m system requires a timing recovery loop which is robust in frequency offset and has fast acquisition because Inmarsat mini-m system specification requires frequency tolerance is required of ${\pm}924$ Hz (signal bandwidth: 2.4 kHz) and acquisition time of UW (Unique Word) signal duration (15ms).Therefore, we propose a timing recovery loop which is suitable for Inmarsat mini-m system. The proposed timing recovery loop adopted noncoherent UW detector and differential ELD which applied differential UW signal for stability and fast acquisition in frequency offset environment. Simulation results show that the proposed timing recovery loop has stable operation and fast acquisition in frequency offset environment for the system.