• Journal of Information Technology Services
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• v.11 no.4
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• pp.251-262
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• 2012

Unit testing is one of the test levels, which tests an individual unit or a group of related units. Recently, in Agile Development or Safety-critical System Development, the unit testing plays an important role for the qualities. According to the definition of unit testing, it is supposed to be done by the developers of units. That is because test models for the unit testing refers to the structure of units, and others but its original developers hardly can understand the structures. However, in practice, unit testing is often asked to be done without the original developers. For example, it is when faults are revealed in customer sites and the development team does not exit any more. In this case, instead of original developers, other developers or test engineers take a product and test it. The unit testing done by a non-developer, who is not the original developer, would cause some difficulties or cause more cost. In this paper, we tests an open source, JTopas, as a non-developer, with building test models, implementing test codes, and executing test cases. To fit this experiment to practical testing situations, we designed it based on the practices of unit testing, which were surveyed through SPIN(Software Process Improvement Network). This paper analyzes which part of unit testing done by non-developers needs more effort compared to the unit testing done by original developers. And it concludes that Agile Development contributes on reducing the extra effort caused by non-developers, since it implements test codes first before developing source code. That means all the units have already included their own tests code when they are released.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.3
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• pp.111-116
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• 2013

With technology scaling, soft error rate has greatly increased in embedded systems. Due to high performance and low power consumption, VLIW (Very Long Instruction Word) architectures have been widely used in embedded systems and thus many researches have been studied to improve the reliability of a system by duplicating instructions in VLIW architectures. However, existing studies have ignored the feature, called VLES (Variable Length Execution Set), which is adopted in most modern VLIW architectures to reduce code size. In this paper, we propose how to support instruction duplication in VLIW architecture with VLES. Our experimental results demonstrate that a VLIW architecture with VLES shows 64% code size decrement on average at the cost of about 4% additional cell area as compared to the case of a VLIW architecture without VLES when instruction duplication is applied to both architectures. Also, it is shown that the case with VLES does not cause extra execution time compared to the case without VLES.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.255-258
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• 1999

This paper describes a 40-Msample/s 10-bit CMOS folding and interpolating analog-to-digital converter (ADC). A new 2-step architecture is proposed. The proposed architecture is composed of a coarse ADC bloch for the 6bits of MSBs and a fine ADC block for the remaining 4bits. The amplified folding analog signals in the coarse ADC are selectively chosen for the fine ADC. In the fine ADC, the bubble errors of the comparators are corrected by using the BGM(binary-gray-mixed) code[1] and extra two comparators are used to correct underflow and overflow errors. The proposed ADC was simulated using CMOS 0.25${\mu}{\textrm}{m}$ parameters and occupies 1.0mm$\times$1.0mm. The power consumption is 48㎽ at 40MS/s with 2.5-V power supply. The INL is under $\pm$2.0LSB and the DNL. is under $\pm$1.0LSB by Matlab simulations.

• 한국전산유체공학회:학술대회논문집
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• 2008.03b
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• pp.228-231
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• 2008

Flow fields of a transonic centrifugal compressor are calculated using the commercial CFD code, CFX-TASCflow. Due to the transonic inlet condition, interactions between the shock wave and boundary layers and between the shock wave and tip leakage vortices generate complex flow structures and extra losses. The calculated results show that strong secondary flows due to high curvature and high rotational speed of the impeller. And streamlines near suction surface show that strong radially upward flow develops after the shock between the leading edge locations of main blade and splitter.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.4
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• pp.401-404
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• 2010

In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.4
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• pp.419-428
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• 1986

While three most important aspects of line codes are the de-free, the minimum-bandwidth, and the self-clocking properties, the only TIBr, VMDBr, RMD3r, RMD4r codes possess all of these properties. This paper is to report the results of an experimental performance study of VMDB5. The encoder and decoder of VMDB5 and the pulse shaper have been inplemented. Power spectra, eye patterns, and error probabilities are experimentally measured, confirming the theoreticla performance predictions. It has been observed that the NRZ pulse shaping reliable transmission is possible with no extra equalization even in teh case when the -3dB channel bandwith is only half the Nyquist bandwidth.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.984-995
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• 1996

Data errors according to the various noises caused in the satellite communication links are corrected by the Viterbi decoding algorithm which has extreme error correcting capability. In this paper, we designed and implemented a convolutional encoder and Viterbi decoder ASIC which is used to encode the input data at the transmit side and correct the errors of the received data at the receive side for use in the VSAT communication system. And this chip may be used in any BPSK, QPSK, or OQPSK transmission system. The ambiguity resolver corrects PSK modem ambiguities by delaying, interting, and/or exchanging code symbol to restore their original sequence and polarity. In case of previous decoding system, ambiguity state(AS) of data is resolved by external control logic and extra redundancy data are needed to resolve AS. But, by adopting decoder proposed in this paper, As of data is resolved automatically by internal logic of decoder in case of continuous mode, and by external As line withoug extra redudancy data in burst mode case. So, decoding parts are simple in continuous mode and transmission efficiency is increased in bust mode. The features of this chip are full duplex operation with independent transmit and receive control and clocks, start/stop inputs for use in burst mode systems, loopback function to verify encoder and decoder, and internal or external control to resolve ambinguity state. For verification of the function and performance of a fabricated ASIC chip, we equiped this chip in the Central and Remote Earth Station of VSAT system, and did the performance test using the commerical INTELSAT VII under the real satellite link environmens. The results of test were demonstrated the superiority of performance.

• Journal of the Korea Safety Management & Science
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• v.12 no.1
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• pp.113-118
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• 2010

"Domestic delivery service" is defined the service to deliver goods or packages from point of senders to point of receiver. With the characteristics of door to door, it is must a service provider should know the exact location of destination assuring best utilization of moving path. Generally, location information consist of postal code and address only, which result in difficulties to identify the precise location of destination. It is relatively less correlated between the information that address refers and practical location in Korea address system. For example, the next door to house number 100 is not always house number 101. Therefore, a delivery man additionally uses a paper map or a GPS navigation which carry extra job to input every code of location to the device in order to know precise location. It is also very inconvenient that every delivery man identify the location that address information refers and make a personal decision of the optimum moving path dropping each destination without calculating provisioning process of whole delivery path. As explained above, it is inefficient to find information delivery service required and to generate the optimum path. In results, these difficulties bring in delay of service and increase of cost. In this point, the contents of the thesis suggest a GPS navigation system easy to obtain accuracy of delivery information which enables to automate optimum moving path based on RFID which contains location information.

• Tunnel and Underground Space
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• v.23 no.1
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• pp.54-65
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• 2013

The LCM (Linear Cutting Machine) test is one of the most powerful and reliable methods for designing the disc cutter and for predicting the TBM (Tunnel Boring Machine) performance. It has an advantage to predict the actual load on disc cutter from the laboratory test on the real-size large rock samples, however, it also has a disadvantage to transport and/or prepare the large rock samples and to need an extra cost for experiment. In order to overcome this problem, lots of numerical studies have been performed. In this study, the PFC3D (Particle Flow Code in 3 Dimension) has been adopted for numerical analysis on optimum cutter spacing and failure aspects of Busan Tuff. The optimum cutting condition with s/p ratio of 16 and minimum specific energy of $14MJ/m^3$ was derived from numerical analyses. The cutter spacing for Busan Tuff had the good agreements with those of LCM test and numerical analysis by finite element method.

• Korean Journal of Computational Design and Engineering
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• v.20 no.2
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• pp.124-132
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• 2015

When Building Information Modeling (BIM) was introduced at the early stage, it was only utilized as a three-dimensional visualization tool. Nowadays, however, BIM is being studied for increasing design productivity and managing enormous information on building life cycle. One of the representative research is developing 'common prototype BIM libraries'. BIM data made of common prototype libraries should be utilized in various ways, quantity takeoff, code checking, energy analysis and so on. However, common prototype BIM libraries are not enough to estimate accurate cost. For example, composite wall libraries should be divided into several single objects, wall structure and finishes, for the quantity takeoff and construction cost calculation. In this paper, we are suggesting an automated division algorithm of composite wall and developing a system prototype for it. This study is expected to reduce extra modeling work and contribute to fast and accurate cost calculation in the construction.