• Title/Summary/Keyword: expected delay

Search Result 452, Processing Time 0.029 seconds

A Study on the Variation of Air Pollutants Emission Rates for Different Traffic Signal System in Metropolitan Area (대도시 교통신호시스템에 따른 대기오염물질 배출량 변화에 관한 연구)

  • 홍민선;우완기;최종인
    • Journal of Korean Society for Atmospheric Environment
    • /
    • v.9 no.1
    • /
    • pp.93-100
    • /
    • 1993
  • This study was carried out to investigate the relationship between the traffic signal systmes and the air pollutants emitted by the motor vehicles at Kangnam Intersection. One of the most important measures of effectiveness (MOE) in traffic studies is the delay to vehicles in the system. Delay represents indirect costs to the motorist in terms of time loss and a direct cost in terms of fuel consumption during idling. The results of TRANSYT-7F modeling was correlated among delay, fuel consumption and total travel tiem. Air pollutants emission rate can be calculated by the results of modeling and the Korean type emission factor. As expected the highest emissions, for air pollutants, are observed during the morning rush hours (07 : 00-10 : 00). For better results of modeling, the TRANSYT-7F model needs to modify for the Korean type of traffic model. The results of this study indicate that the variation of air pollutants emission rates were closely related to the traffic signal system.

  • PDF

Failure Analysis of BGA Test Socket Pins (BGA 검사 소켓 핀의 불량 분석 연구)

  • Kim, Myung-Sik;Bae, Kyoo-Sik
    • Korean Journal of Materials Research
    • /
    • v.18 no.9
    • /
    • pp.497-502
    • /
    • 2008
  • BGA test sockets failed earlier than the expected life-time due to abnormal signal delay, shown especially at the low temperature ($-50^{\circ}C$). Analysis of failed sockets was conducted by EDX, AES, and XRD. A SnO layer contaminated with C was found to form on the surface of socket pins. The formation of SnO layer was attributed to the repeated Sn transfer from BGA balls to pin surface and instant oxidation of fresh Sn. As a result, contact resistance increased, inducing signal delay. Abnormal signal delay at the low temperature was attributed to the increasing resistivity of Sn oxide with decreasing temperature, as manifested by the resistance measurement of $SnO_2$.

A switching-based delay optimal aggregation tree construction: An algorithm design (에이전트 시스템 개발도구에 관한 연구)

  • Nguyen, Dung T.;Yeom, Sanggil;Choo, Hyunseung
    • Proceedings of the Korea Information Processing Society Conference
    • /
    • 2017.04a
    • /
    • pp.677-679
    • /
    • 2017
  • Data convergecast is an indispensable task for any WSN applications. Typically, scheduling in the WSN consists of two phases: tree construction and scheduling. The optimal tree structure and scheduling for the network is proven NP-hard. This paper focuses on the delay optimality while constructing the data convergecast tree. The algorithm can take any tree as the input, and by performing the switches (i.e. a node changes its parent), the expected aggregation delay is potentially reduced. Note that while constructing the tree, only the in-tree collisions between the child nodes sending data to their common parent is considered.

Risk Evaluation of Failure Cause for FMEA under a Weibull Time Delay Model (와이블 지연시간 모형 하에서의 FMEA를 위한 고장원인의 위험평가)

  • Kwon, Hyuck Moo;Lee, Min Koo;Hong, Sung Hoon
    • Journal of the Korean Society of Safety
    • /
    • v.33 no.3
    • /
    • pp.83-91
    • /
    • 2018
  • This paper suggests a weibull time delay model to evaluate failure risks in FMEA(failure modes and effects analysis). Assuming three types of loss functions for delayed time in failure cause detection, the risk of each failure cause is evaluated as its occurring frequency and expected loss. Since the closed form solution of the risk metric cannot be obtained, a statistical computer software R program is used for numerical calculation. When the occurrence and detection times have a common shape parameter, though, some simple results of mathematical derivation are also available. As an enormous quantity of field data becomes available under recent progress of data acquisition system, the proposed risk metric will provide a more practical and reasonable tool for evaluating the risks of failure causes in FMEA.

A dynamic multicast routing algorithm in ATM networks (ATM 망에서 동적 멀티캐스트 루팅 알고리즘)

  • 류병한;김경수;임순용
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.22 no.11
    • /
    • pp.2477-2487
    • /
    • 1997
  • In this paepr, we propose a dynamic multicast routin algorithm for constructing the delay-constrained minimal spanning tree in the VP-based ATM networks, in which we consider the effiiciency enen in the case wheree the destination dynamically joins/departs the multicast connection. For constructing the delay-constrained spanning tree, we frist generate a reduced network consisting of only VCX nodes from a given ATM network, originally consisting of VPX/VCX nodes. Then, we obtain the delay-constrained spanning tree with a minimal tree cost on the reduced network by using our proposed heuristic algorithm. Through numerical examples, we show that our dynamic multicast routing algorithm can provide an efficient usage of network resources when the membership nodes frequently changes during the lifetime of a multicast connection. We also demonstrate the more cost-saving can be expected in dense networks when applyingour proposed algorithm.

  • PDF

Study on the Measurement-Based Packet Loss Rates Assuring for End-to-End Delay-Constrained Traffic Flow (지연 제한 트래픽 흐름에 대한 측정 기반 패킷 손실률 보장에 관한 연구)

  • Kim, Taejoon
    • Journal of Korea Multimedia Society
    • /
    • v.20 no.7
    • /
    • pp.1030-1037
    • /
    • 2017
  • Traffic flows of real-time multimedia services such as Internet phone and IPTV are bounded on the end-to-end delay. Packets violating their delay limits will be dropped at a router because of not useful anymore. Service providers promise the quality of their providing services in terms of SLA(Service Level Agreement), and they, especially, have to guarantee the packet loss rates listed in the SLA. This paper is about a method to guarantee the required packet loss rate of each traffic flow keeping the high network resource utilization as well. In details, it assures the required loss rate by adjusting adaptively the timestamps of packets of the flow according to the difference between the required and measured loss rates in the lossy Weighted Fair Queuing(WFQ) scheduler. The proposed method is expected to be highly applicable because of assuring the packet loss rates regardless of the fluctuations of offered traffic load in terms of quality of services and statistical characteristics.

Flow Assignment and Packet Scheduling for Multipath Routing

  • Leung, Ka-Cheong;Victor O. K. Li
    • Journal of Communications and Networks
    • /
    • v.5 no.3
    • /
    • pp.230-239
    • /
    • 2003
  • In this paper, we propose a framework to study how to route packets efficiently in multipath communication networks. Two traffic congestion control techniques, namely, flow assignment and packet scheduling, have been investigated. The flow assignment mechanism defines an optimal splitting of data traffic on multiple disjoint paths. The resequencing delay and the usage of the resequencing buffer can be reduced significantly by properly scheduling the sending order of all packets, say, according to their expected arrival times at the destination. To illustrate our model, and without loss of generality, Gaussian distributed end-to-end path delays are used. Our analytical results show that the techniques are very effective in reducing the average end-to-end path delay, the average packet resequencing delay, and the average resequencing buffer occupancy for various path configurations. These promising results can form a basis for designing future adaptive multipath protocols.

The timing do-skew modeling and design in a high speed digital system (고속 디지털 시스템에서 전달 시간차의 보정 모델링 및 구현)

  • Oh, Kwang-Suhk
    • Proceedings of the KIEE Conference
    • /
    • 2002.11c
    • /
    • pp.601-604
    • /
    • 2002
  • In this paper, the timing do-skew modeling for a high speed logic tester channels is developed. The time delay of each channel in a logic tester are different from other channels and it can produce timing error in a test. To get the best timing accuracy in the test with a logic tester, the timing skew must be compensated. The timing skew of channels is due to the difference of time delay of pin-electronics devices composing channels and length of metal line placed on PCB. The expected timing difference of channels can be calculated according to the specifications of pin electronics devices and strip line modeling of PCB. With the calculated delay time, the timing skew compensation circuit has been designed. With the timing skew compensation circuit, the timing calibration of a logic tester can be peformed easily and automatically without other time measuring instruments. The calibration method can then be directly applied to logic testers in mass production lines.

  • PDF

Latency Analysis of AVB Network and Optimization Design for Automotive

  • An, Byoungman;Kim, YoungSeop
    • Journal of the Semiconductor & Display Technology
    • /
    • v.18 no.3
    • /
    • pp.127-132
    • /
    • 2019
  • This paper presents an overview of automotive communication technologies, including related technology developments. We describe the latency of Audio Video Bridge (AVB) network as well as purpose the optimized design of the Ethernet network system for automotive. Our design plays a significant role in reducing the delay between components. The proposed approach on realistic test cases showed that there was a delay reduction, approximately 49.4%. It is expected that the optimization method for the actual automotive environment can greatly shorten the time period in the design and development process. The results obtained from the experiments on the delay time present in each function are reliable because average values are obtained through repeated actual tests for several months. It will greatly benefit the industry since analyzing the latency between each function in a short period of time is very important.

Implementation of a High Performance XOR-XNOR Circuit

  • Kim, Jeong-Beom
    • The Journal of the Korea institute of electronic communication sciences
    • /
    • v.17 no.2
    • /
    • pp.351-356
    • /
    • 2022
  • The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.