• Interaction and multiscale mechanics
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• v.6 no.2
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• pp.197-210
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• 2013

A fundamental trend of processor architecture evolving towards exaflops is fast increasing floating point performance (so-called "free" flops) accompanied by much slowly increasing memory and network bandwidth. In order to fully enjoy the "free" flops, a numerical algorithm of PDEs should request more flops per byte or increase arithmetic intensity. A meshfree/GFEM approximation can be the class of the algorithm. It is shown in a GFEM without extra dof that the kind of approximation takes advantages of the high performance of manycore GPUs by a high accuracy of approximation; the "expensive" method is found to be reversely hardware-efficient on the emerging architecture of manycore.

• The Journal of the Korea Contents Association
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• v.21 no.2
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• pp.641-651
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• 2021

Supercomputers have played an important role in various fields such as science, industry, national security and solutions for social issues, and their demand is increasing significantly as their use is strengthened in areas using big data and AI. Recently, competition for global exascale system development is accelerating based on various architectures, and the era of exascale computing is expected to come in the near future. However, the foundation of the domestic supercomputing ecosystem was lost due to the decline of the server industry in the past, and although the related law was enacted to supplement and foster it, it has not been able to perform its function smoothly. Therefore, this article examines the problems in the current legal system through the analysis of the relevant legal system and the status of the supercomputing ecosystem, and suggests improvements so that the relevant legal system, which can accommodate the reinforcement of the role of the government·national center·professional center, support for industries, promotion of commercialization of research results, and flexibility of government promotion policies, can prepare the basis for the promotion of the supercomputing R&D project.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.82-90
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• 2013

An Optical Network-on-Chip(ONoC) based on silicon photonics is one of promising technology for next generation exascale computing architectures. Recent active researches on ONoC focus on improving bandwidth further and avoiding path collisions by using wavelength division multiplexing (WDM). However, the number of wavelengths used for the WDM increases linearly as the number of Processing Element (PE) increases in existing ONoCs which adopt centralized routing architecture. The problem will also arises growing cost of optical devices such as light switches and light sources and limits the scalability of ONoC due to the sinal loss caused by interference of distinct light sources. In this paper, we proposes a distributed routing architecture for ONoC which is based on 2D-mesh structure using WDM technique and present a method that minimize the required number of wavelengths exploiting the connectivity of communication. In comparison with existing centralized routing architectures, results show reduction by 56% of the number of wavelengths and 21% of the number of optical switches in $8{\times}8$ networks.

• KIPS Transactions on Software and Data Engineering
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• v.2 no.2
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• pp.81-90
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• 2013

During the past decade, many changes and attempts have been tried and are continued developing new technologies in the computing area. The brick wall in computing area, especially power wall, changes computing paradigm from computing hardwares including processor and system architecture to programming environment and application usage. The high performance computing (HPC) area, especially, has been experienced catastrophic changes, and it is now considered as a key to the national competitiveness. In the late 2000's, many leading countries rushed to develop Exascale supercomputing systems, and as a results tens of PetaFLOPS system are prevalent now. In Korea, ICT is well developed and Korea is considered as a one of leading countries in the world, but not for supercomputing area. In this paper, we describe architecture design of MAHA supercomputing system which is aimed to develop 300 TeraFLOPS system for bio-informatics applications like human genome analysis and protein-protein docking. MAHA supercomputing system is consists of four major parts - computing hardware, file system, system software and bio-applications. MAHA supercomputing system is designed to utilize heterogeneous computing accelerators (co-processors like GPGPUs and MICs) to get more performance/$, performance/area, and performance/power. To provide high speed data movement and large capacity, MAHA file system is designed to have asymmetric cluster architecture, and consists of metadata server, data server, and client file system on top of SSD and MAID storage servers. MAHA system softwares are designed to provide user-friendliness and easy-to-use based on integrated system management component - like Bio Workflow management, Integrated Cluster management and Heterogeneous Resource management. MAHA supercomputing system was first installed in Dec., 2011. The theoretical performance of MAHA system was 50 TeraFLOPS and measured performance of 30.3 TeraFLOPS with 32 computing nodes. MAHA system will be upgraded to have 100 TeraFLOPS performance at Jan., 2013.

• Journal of Information Science Theory and Practice
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• v.10 no.spc
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• pp.56-65
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• 2022

Korea Institute of Science and Technology Information (KISTI) is a Worldwide LHC Computing Grid (WLCG) Tier-1 center mandated to preserve raw data produced from A Large Ion Collider Experiment (ALICE) experiment using the world's largest particle accelerator, the Large Hadron Collider (LHC) at European Organization for Nuclear Research (CERN). Physical medium used widely for long-term data preservation is tape, thanks to its reliability and least price per capacity compared to other media such as optical disk, hard disk, and solid-state disk. However, decreasing numbers of manufacturers for both tape drives and cartridges, and patent disputes among them escalated risk of market. As alternative to tape-based data preservation strategy, we proposed disk-only erasure-coded archival storage system, Custodial Disk Storage (CDS), powered by Exascale Open Storage (EOS), an open-source storage management software developed by CERN. CDS system consists of 18 high density Just-Bunch-Of-Disks (JBOD) enclosures attached to 9 servers through 12 Gbps Serial Attached SCSI (SAS) Host Bus Adapter (HBA) interfaces via multiple paths for redundancy and multiplexing. For data protection, we introduced Reed-Solomon (RS) (16, 4) Erasure Coding (EC) layout, where the number of data and parity blocks are 12 and 4 respectively, which gives the annual data loss probability equivalent to 5×10^-14. In this paper, we discuss CDS system design based on JBOD products, performance limitations, and data protection strategy accommodating EOS EC implementation. We present CDS operations for ALICE experiment and long-term power consumption measurement.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.11-19
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• 2015

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.