• Title/Summary/Keyword: error structure

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Performance Improvement of a 6-Axis Force-torque Sensor via Novel Electronics and Cross-shaped Double-hole Structure

  • Kang Chul-Goo
    • International Journal of Control, Automation, and Systems
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    • v.3 no.3
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    • pp.469-476
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    • 2005
  • Performance of a force-torque sensor is affected significantly by an error signal that is included in the sensor signal. The error sources may be classified mainly into two categories: one is a structural error due to inaccuracy of sensor body, and the other is a noise signal existing in sensed information. This paper presents a principle of 6-axis force-torque sensor briefly, a double-hole structure to be able to improve a structural error, and then a signal conditioning to reduce the effect of a noise signal. The validity of the proposed method is investigated through experimental study, which shows that SIN ratio is improved significantly in our experimental setup, and the sensor can be implemented cheaply with reasonable performance.

[ ${\pi}/4$ ] shift QPSK for NEC structure in multipath channels (멀티패스 채널 환경하에서 NEC 구조를 이용한 ${\pi}/4$ shift QPSK)

  • Pyeon, Yong-Kug;Kang, Ki-Sung;Yim, Hwang-Bin;Shim, Sang-Heung;Yoon, Sang-Ok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07b
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    • pp.1212-1216
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    • 2003
  • In this study, the ${\pi}/4$ shift QPSK(quadrature phase shift keying) with NEC(nonredundant error correction) on the multipath channel can detect the burst error as well as random error one by using the second and L-th order phase difference. Therefore, the BER(bit error rate) performance in ${\pi}/4$ shift QPSK is more improved than that of the ${\pi}/4$ shift QPSK without NEC structure. Also, this performance become a bit better in Rayleigh fading channel.

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A Sensorless Vector Control System for Induction Motors Using Stator Current Difference

  • Park, Chul-Woo;Choi, Byeong-Tae;Kwon, Woo-Hyen;Ku, Bon-Ho;Youn, Kyung-Sub
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.139.4-139
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    • 2001
  • The thesis propose the sensorless vector control method that estimates the rotor speed using stator current. The estimated speed is used as feedback in a vector control system. The conventional MRAS structure has a problem the error output is decreasing as estimated speed error is increasing and the estimation performance is not robust when mutual inductance has been changed. In the proposed method, error output is proportional to estimated speed error. The described technique is less complex, robust to variations of mutual inductance. This new method can achieve much wider bandwidth speed control than that of the conventional MRAS structure.

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Structural Convergence Improvement Schemes on Adaptive Control Redesigning a Lyapunov's Function (Lyapunov 함수를 재설계한 적응제어외의 구조적 수렴향상 방법에 대한 연구)

  • Kang, Hoon
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.1
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    • pp.1-9
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    • 1989
  • The convergence analysis of adavtive control schemes has been studied over the past decades, but the importance of structure to fast conversgece of adaptive control systems is still a controversial issue. This paper deals with the relative improvement of the exponential rate of convergence in adaptive error models. The Lyapunov's direct method is applied to adaptive control systems in order to improve the convergence rate by modifying the feedback structure of the error systems. Some simulation examples are illustrated to show fast convergence and robustness of these schemes.

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Decision of SSI Network dimension for Safety based ODLM(LDT) installation (안전성 기반 ODLM(LDT) 설치를 위한 SSI 네트워크 규모 결정)

  • Min, Geun-Hong;Lee, Jong-Woo
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.5
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    • pp.797-802
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    • 2008
  • High Speed Rail Train Control System consists of CTC, IXL and ATC. IXL and ATC perform train control and command via interchanging relevant information between a signal room and CTC. However, it is proved that IXL and ATC are attributed to train delay error since those systems are highly sensitive to trackside conditions. Especially, network error on IXL blocks transmitting signal information to adjacent signal room so that its effects give rise to system overall problems. In order to figure out the measures for which minimizing the occurrence rate of train delay error due to HSR TCS, This paper is performed analysis on communication network structure, the length of SSI network roof and SSI-TFM distance by examining and analyzing the error cases related to IXL in a network aspect.

Effects of Dimension of Part and Structure of Supports on the Shape Error in Stereolithography Process (SL 광조형 공정에서 제작물 치수와 지지대 구조가 형상오차에 미치는 영향)

  • Kim, Gi-Dae
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.15 no.3
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    • pp.32-38
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    • 2006
  • During stereolithography processes, the shape errors such as curl distortion and distortion of side face are generated due to the shrinkage of liquid resins. In this study, the effects of dimension of part and structure of supports on the shape error are examined. Cubic specimens which have different thicknesses are manufactured and their deformations are measured with CMM. Thicker part generates smaller curl distortion of top face and larger of bottom face. Also thicker part generates larger distortion of side face until part thickness increases to about 20mm. Larger stiffness of supports which is obtained by shorter spacing of the supports and line type contact instead of point type contact generates smaller shape error of the part.

Built-In Self-Test of DAC using CMOS Structure (CMOS 구조를 이용한 DAC의 자체 테스트 기법에 관한 연구)

  • Cho, Sung-Chan;Kim, In-Soo;Min, Hyoung-Bok
    • Proceedings of the KIEE Conference
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    • 2007.07a
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    • pp.1862-1863
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    • 2007
  • Testing the analog/mixed-signal circuitry of a mixed-signal IC has become a difficult task. Offset error, gain error, Non-monotonic behavior, Differential Non-linearity(DNL) error, Integral Non-linearity(INL) error are important specifications used as test parameters for DAC. In this paper, we propose an efficient BIST structure for DAC testing. The proposed BIST adds the circuit which uses the capacitor and op-amp, and accomplishes a test.

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An Analysis of Human Error Mode and Type in the Railway Accidents and Incidents (철도 사고 및 장애의 인적오류 유형 분석)

  • Ko, Jong-Hyun;Jung, Won-Dea;Kim, Jae-Whan
    • Journal of the Korean Society of Safety
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    • v.22 no.4
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    • pp.66-71
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    • 2007
  • Human error is one of the major contributors to the railway accidents or incidents. In order to develop an effective countermeasure to remove or reduce human errors, a systematic analysis should be preferentially performed to identify their causes, characteristics, and types of human error induced in accidents or incidents. This paper introduces a case study for human error analysis of the railway accidents and incidents. For the case study, more than 1,000 domestic railway accidents or incidents that happened during the year of 2004 have been investigated and a detailed error analysis was performed on the selected 90 cases, which were obviously caused by human error. This paper presents a classification structure for human error analysis, and summarizes the analysis results such as causes of the events, error modes and types, related worker, and task type.

Floating-Poing Quantization Error Analysis in Subband Codes System

  • Park, Kyu-Sik
    • The Journal of the Acoustical Society of Korea
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    • v.16 no.1E
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    • pp.41-48
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    • 1997
  • The very purpose of subband codec is the attainment of data rate compression through the use of quantizer and optimum bit allocation for each decimated signal. Yet the question of floating-point quantization effects in subband codec has received scant attention. There has been no direct focus on the analysis of quantization errors, nor on design with quantization errors embedded explicitly in the criterion. This paper provides a rigorous theory for the modelling, analysis and optimum design of the general M-band subband codec in the presence of the floating-point quantization noise. The floating-point quantizers are embedded into the codec structure by its equivalent multiplicative noise model. We then decompose the analysis and synthesis subband filter banks of the codec into the polyphase form and construct an equivalent time-invariant structure to compute exact expression for the mean square quantization error in the reconstructed an equivalent time-invariant structure to compute exact expression for the mean square quantization error in the reconstructed output. The optimum design criteria of the subband codec is given to the design of the analysis/synthesis filter bank and the floating-point quantizer to minimize the output mean square error. Specific optimum design examples are developed with two types of filter of filter banks-orthonormal and biorthogonal filter bank, along with their perpormance analysis.

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Reliability on Accelerated Soft Error Rate in Static RAM of Thin Film Transistor Type (소프트 에러율에 대한 박막 트랜지스터형 정적 RAM의 신뢰성)

  • Kim Do-Woo;Wang Jin-Suk
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.19 no.6
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    • pp.507-511
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    • 2006
  • We investigated accelerated soft error rate (ASER) in static random access memory (SRAM) cells of thin film transistor (TFT) type. The effects on ASER by cell density, buried nwell structure, operational voltage, and polysilicon-2 layer thickness were examined. The increase in the operational voltage, and the decrease in the density of SRAM cells, respectively, resulted in the decrease of ASER values. The SRAM chips with buried nwell showed lower ASER than those with normal well structure did. The ASER decreased as the test distance from alpha source to the sample increased from $7{\mu}m\;to\;15{\mu}m$. As the polysilicon-2 thickness increased up to $1000\;{\AA}$, the ASER decreased exponentially. In conclusion, the best condition for low soft error rate, which is essential to obtain highly reliable SRAM device, is to apply the buried nwell structure scheme and to fabricate thin film transistors with the thick polysilicon-2 layer