• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.25-32
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• 2014

In this paper, we proposed a partial-way set associative cache memory with an effective memory access time and low energy consumption. In the proposed set-associative cache memory, it is allowed to access only a 2-ways among 4-way at a time. Choosing ways to be accessed is made dynamically via the least significant two bits of the tag. The chosen 2 ways are sequentially accessed by the way selection bits that indicate the most recently referred way. Therefore, each entry in the way has an additional bit, that is, the way selection bit. In addition, instead of the 4-way LRU or FIFO algorithm, we can utilize a simple 2-way replacement policy. Simulation results show that the energy*delay product can be reduced by about 78%, 14%, 39%, and 15% compared with a 4-way set associative cache, a sequential-way cache, a way-tracking cache, and a way cache respectively.

• Restorative Dentistry and Endodontics
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• v.33 no.5
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• pp.428-434
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• 2008

The purpose of this study was to compare the microtensile bond strength in Class I cavities associated with different light curing modes of same light energy density. Occlusal enamel was removed to expose a flat dentin surface and twenty box-shaped Class I cavities were prepared in dentin. Single Bond (3M Dental product) was applied and Z 250 was inserted using bulk technique. The composite was light-cured using one of four techniques, pulse delay (PD group), soft-start (SS group), pulse cure (PC group) and standard continuous cure (CC group). The light-curing unit capable of adjusting time and intensity (VIP, Bisco Dental product) was selected and the light energy density for all curing modes was fixed at $16J/cm^2$. After storage for 24 hours, specimens were sectioned into beams with a rectangular cross-sectional area of approximately $1mm^2$ Microtensile bond strength $({\mu}TBS)$ test was per- formed using a univel·sal testing machine (EZ Test, Shimadzu Co.). The results were analyzed using oneway ANOVA and Tukey's test at significance level 0.05. The ${\mu}TBS$ of PD group and SS group was higher than that of PC group and CC group. Within the limitations of this in vitro study, modification of curing modes such as pulse delay and soft start polymerization can improve resin/dentin bond strength in Class I cavities by controlling polymerization velocity of composite resin.

• Journal of Communications and Networks
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• v.16 no.5
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• pp.479-484
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• 2014

In this paper, we consider the construction of cyclic and quasi-cyclic structured q-ary low-density parity-check (LDPC) codes over a designated small field. The construction is performed with a pre-defined sliding-window, which actually executes the regular mapping from original field to the targeted field under certain parameters. Compared to the original codes, the new constructed codes can provide better flexibility in choice of code rate, code length and size of field. The constructed codes over small fields with code length from tenths to hundreds perform well with q-ary sum-product decoding algorithm (QSPA) over the additive white Gaussian noise channel and are comparable to the improved spherepacking bound. These codes may found applications in wireless sensor networks (WSN), where the delay and energy are extremely constrained.

• Journal of Electrical Engineering and Technology
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• v.11 no.2
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• pp.353-360
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• 2016

Series hybrid electric vehicles (SHEVs) having multiple power sources such as an engine- generator (EnGen), a battery, and an ultra-capacitor require a power control unit with high power density and reliable control operation. However, manufacturing using separate individual power converters has the disadvantage of low power density and requires a large number of power and signal cable wires. It is also difficult to implement the optimal power distribution and fault management algorithm because of the communication delay between the units. In order to address these concerns, this approach presents a design methodology and a power control algorithm of an integrated power converter for the SHEVs powered by multiple power sources. In this work, the design methodology of the integrated power control unit (IPCU) is firstly elaborately described, and then efficient and reliable power distribution algorithms are proposed. The design works are verified with product-level and vehicle-level performance experiments on a 10-ton SHEV.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.4
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• pp.201-207
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• 2012

Currently, NAND Flash memory has been widely used in consumer storage devices due to its non-volatility, stability, economical feasibility, low power usage, durability, and high density. However, a high capacity of NAND flash memory causes the high power consumption and the low performance. In the convention memory research, a hierarchical filter mechanism can archive an effective performance improvement in terms of the power consumption. In order to attain the best filter structure for NAND flash memory, we selected a direct-mapped filter, a victim filter, a fully associative filter and a 4-way set associative filter for comparison in the performance analysis. According to the results of the simulation, the fully associative filter buffer with a 128byte fetching size can obtain the bet performance compared to another filter structures, and it can reduce the energy*delay product(EDP) by about 93% compared to the conventional NAND Flash memory.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.967-970
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• 2003

A new adder-and-accumulator (A$^2$C) adapted to pipelined Δ$\Sigma$ modulators is proposed in this paper. With the viewpoint of area consumption, registers are removed in the existing pipelined Δ$\Sigma$ modulator, and then adder and accumulator are merged. In order to optimize area consumption, speed and power consumption, dynamic carry look-ahead adder (CLA) is adopted in $A^2$C. Moreover, a guideline for the transistor sizing in CLA with regard to the minimization of the energy-delay-area product (EDAP) is proposed[1]. The proposed $A^2$C has been verified by HSPICE simulations.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.223-225
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• 2003

본 논문은 서로 다른 두 구조의 캐쉬와 새로운 뱅크선별기를 이용하여, 보다 효율적인 뱅크관리 메커니즘을 응용한 새로운 개념의 캐쉬 구조에 대한 설명을 한다. 크기가 작음에도 불구하고, 낮은 접근 실패율(Miss ratio)와 높은 저전력 효과는 기존의 일반적인 직접사상 캐쉬와 비교했을 때, 성능면에서 월등한 차이를 나타내고 있다. 이러한 결과의 원인은 직접사상 캐쉬와 완전연관 버퍼의 최적화된 구성과. 효과적인 뱅크선별기를 사용하여 적은 전력에도 높은 성능을 발휘하는 새로운 메커니즘을 사용하였기 때문이다. 제안한 구조의 성능은 다양한 크기의 직접사상 캐쉬와 비교하였으며, 접근 실패율, 평균 메모리 접근 시간, 전력소비, Energy * Delay Product 등 모두 4가지의 지표를 사용하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.180-183
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• 2013

근래의 프로세서는 하나의 다이 위에 여러 개의 코어를 배치한 멀티코어 형태를 띠고 있다. 최근에는 프로세서의 에너지 소비량을 줄이기 위해 비대칭 멀티코어를 활용하여 동일한 성능을 유지하며 소비전력을 낮추는 방법에 대한 연구가 활발히 진행되고 있다. 비대칭 멀티코어의 장점을 최대한 활용하기 위해서는 대칭형 멀티코어와는 달리 실행해야 할 프로세스와 상이한 코어간의 작동 특성을 고려해야 한다. 본 논문에서는 전력 소비 효율 향상을 위해 프로세스 스케줄링 알고리즘에 하이브리드 인공지능 기술인 Adaptive Neuro Fuzzy Inference System (ANFIS)를 적용하여 각 프로세스에 적합한 코어를 찾아 할당하는 방법을 제안한다. 시뮬레이션 결과 제안하는 프로세스 스케줄러는 리눅스의 CFS 대비 평균 35.4% 낮은 Energy Delay Product (EDP)를 보였으며 이를 통해 하이브리드 인공지능을 적용한 프로세스 스케줄링 알고리즘의 유효성을 입증하였다.

• Asian Pacific Journal of Cancer Prevention
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• v.15 no.23
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• pp.10057-10059
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• 2015

Positron emission tomography (PET) as the functional component of current hybrid imaging (like PET/CT or PET/MRI) seems to dominate the horizon of medical imaging in coming decades. $^{18}$Flourodeoxyglucose ($^{18}FDG$) is the most commonly used probe in oncology and also in cardiology and neurology around the globe. However, the major capital cost and exorbitant running expenditure of low to medium energy cyclotrons (about 20 MeV) and radiochemistry units are the seminal reasons of low number of cyclotrons but mushroom growth pattern of PET scanners. This fact and longer half-life of $^{18}F$ (110 minutes) have paved the path of a centralized model in which $^{18}FDG$ is produced by commercial PET radiopharmacies and the finished product (multi-dose vial with tungsten shielding) is dispensed to customers having only PET scanners. This indeed reduced the cost but has limitations of dependence upon timely arrival of daily shipments as delay caused by any reason results in cancellation or rescheduling of the PET procedures. In recent years, industry and academia have taken a step forward by producing low energy, table top cyclotrons with compact and automated radiochemistry units (Lab-on-Chip). This decentralized strategy enables the users to produce on-demand doses of PET probe themselves at reasonably low cost using an automated and user-friendly technology. This technological development would indeed provide a real impetus to the availability of complete set up of PET based molecular imaging at an affordable cost to the developing countries.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.