Adder-and-Accumulator ($A^{2}C$) for Pipelined $\Delta\Sigma$ Modulator

Pipelined $\Delta\Sigma$ 변조기에 적합한 Adder-and-Accumulator ($A^{2}C$)

A new adder-and-accumulator (A$^2$C) adapted to pipelined Δ$\Sigma$ modulators is proposed in this paper. With the viewpoint of area consumption, registers are removed in the existing pipelined Δ$\Sigma$ modulator, and then adder and accumulator are merged. In order to optimize area consumption, speed and power consumption, dynamic carry look-ahead adder (CLA) is adopted in $A^2$C. Moreover, a guideline for the transistor sizing in CLA with regard to the minimization of the energy-delay-area product (EDAP) is proposed[1]. The proposed $A^2$C has been verified by HSPICE simulations.