• Journal of Internet Computing and Services
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• v.10 no.5
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• pp.195-209
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• 2009

The embedded software has been become more important than the hardware in mobile systems in ubiquitous society. The improvement models such as CMMI(Capability Maturity Model Integration) and SPICE(Software Process Improvement and Capability dEtermination) are used to improve the quality of software in general systems. Software process improvement is also necessary for mobile embedded software development to improve its quality. It is not easy to apply the general software improvement model to the mobile embedded software development due to the high cost effectiveness and heavy process. On the other hand, XP has the characteristics on focused communications with customers and iteration development. It is specially suitable for mobile embedded software development as depending on customer's frequent requirement changes and hardware attributes. In this paper, we propose a framework for development small process improvement based XP(eXtreme Programming)'s practice in order to accomplish CMMI level 2 or 3 in mobile embedded software development at the small organizations. We design and implement the Mobile Embedded Software Process Improvement System(MESPIS) to support process improvement. We also suggest the evaluation method for the mobile embedded software development process improvement framework with CMMI coverage check by comparing other process improvement model. In the future, we need to apply this proposed framework to real project for practical effectiveness and the real cases quantitative. It also include the enhance the functionality of MESPIS.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.6
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• pp.2648-2668
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• 2016

Modern mobile devices are equipped with various accelerated processing units to handle computationally intensive applications; therefore, Open Computing Language (OpenCL) has been proposed to fully take advantage of the computational power in heterogeneous systems. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes on an embedded heterogeneous platform using an OpenCL framework. The LDPC code is one of the most popular and strongest error correcting codes for mobile communication systems. Each step of LDPC decoding has different parallelization characteristics. In the proposed LDPC decoder, steps suitable for task-level parallelization are executed on the multi-core central processing unit (CPU), and steps suitable for data-level parallelization are processed by the graphics processing unit (GPU). To improve the performance of OpenCL kernels for LDPC decoding operations, explicit thread scheduling, vectorization, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance and high power efficiency by using heterogeneous multi-core processors on a unified computing framework.

• Journal of Internet Computing and Services
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• v.6 no.1
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• pp.65-72
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• 2005

Flash memories are one of best media to support portable computers in mobile computing environment. The features of non-volatility, low power consumption. and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However. we need to Improve traditional transaction management scheme due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal. we devise a new scheme called flash-aware transaction management (FATM). FATM improves transaction performance by exploiting SRAM and W-Cache, We also propose a simulation model to show the performance of FATM. Based on the results of the performance evaluation, we conclude that FATM scheme outperforms the traditional scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.49-56
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• 2005

In this paper, we propose a memory BIST Circuit Creation System which creates BIST circuit based on user defined fault model and generates the optimized march test algorithm. Traditional tools have some limit that regenerates BIST circuit after changing the memory type or test algorithm. However, this proposed creation system can automatically generate memory BIST circuit which is suitable in the various memory type and apply algorithm which is required by user. And it gets more efficient through optimizing algorithms for fault models which is selected randomly according to proposed nile. In addition, it support various address width and data and consider interface of IEEE 1149.1 circuit.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11b
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• pp.463-465
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• 2005

내장형 시스템의 요구사항이 복잡해짐에 따라 신뢰성이 높은 소프트웨어 생산이 어려워지고 있다. 본 논문은 신뢰성 높은 내장형 시스템의 소프트웨어를 생산을 위해 교차 컴파일 환경에서 사용 가능한 소프트웨어 테스팅 도구를 제안한다. 일반적으로 테스팅 도구는 독자적인 테스트 스크립트를 사용한다. 그러므로 테스팅을 하고자하는 개발자는 테스팅 도구에서 사용하는 테스트 스크립트를 학습하여야한다. 즉, 개발자가 기존의 테스트 도구를 사용하기 위해서는 새로운 스크립트 언어를 학습해야 하는 부담을 가지고 있다. 본 논문에서 제안하는 시스템은 이러한 단점을 극복하기 위해서 개발자에게 친숙한 XML을 이용하여 테스트 스크립트를 설계한다. XML은 마크 업 언어의 표준으로 다양한 응용을 가지고 있고 다른 형태의 포맷으로 쉽게 변환 가능하다는 장점을 가지고 있다. 또한, GUI 기반의 테스트 스크립트 생성기를 제공하여 개발자에게 직관적인 테스트 스크립트 작성을 할 수 있도록 제안한다. 그리고 기존의 테스트 스크립트와 달리 테스트 스크립트 언어 레벨에서의 테스트 분기를 제공하고 있어 테스트 결과에 따른 다양한 테스트를 실시할 수 있다. 본 테스팅 도구는 개발자에게 테스트 드라이버 작성을 위한 노력을 줄여 더욱 질 좋은 프로그램을 생성하는데 기여할 것으로 기대된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.45-54
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• 2002

This paper proposes serial test data compression, a novel DFT scheme for embedded cores in SOC. To reduce test data amounts, share bit compression and fault undetectable fault pattern compression techniques was used. A Circuits using serial test data compression method are derived from a scan DFT method including a test-per-clock technique. For an experiment of the proposed compression method, full scan versions of ISCASS85 and ISCASS89 were used. ATALANTA has been used for ATPG and fault simulation. The amount of test data has been reduced by maximum 98% comparing with original data.

• Journal of information and communication convergence engineering
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• v.20 no.3
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• pp.166-173
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• 2022

Recently, studies have been conducted on intelligent transportation systems (ITS) that provide safety and convenience to humans. Systems that compose the ITS adopt architectures that applied the cloud computing which consists of a high-performance general-purpose processor or graphics processing unit. However, an architecture that only used the cloud computing requires a high network bandwidth and consumes much power. Therefore, applying edge computing to ITS is essential for solving these problems. In this paper, we propose an edge artificial intelligence (AI) device based ITS. Edge AI which is applicable to various systems in ITS has been applied to license plate recognition. We implemented edge AI on a field-programmable gate array (FPGA). The accuracy of the edge AI for license plate recognition was 0.94. Finally, we synthesized the edge AI logic with Magnachip/Hynix 180nm CMOS technology and the power consumption measured using the Synopsys's design compiler tool was 482.583mW.

• International Journal of Computer Science & Network Security
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• v.23 no.8
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• pp.63-76
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• 2023

Identity and access management in cloud computing is one of the leading significant issues that require various security countermeasures to preserve user privacy. An authentication mechanism is a leading solution to authenticate and verify the identities of cloud users while accessing cloud applications. Building a secured and flexible authentication mechanism in a cloud computing platform is challenging. Authentication techniques can be combined with other security techniques such as intrusion detection systems to maintain a verifiable layer of security. In this paper, we provide an interactive, flexible, and reliable multi-factor authentication mechanisms that are primarily based on a proposed Authentication Method Selector (AMS) technique. The basic idea of AMS is to rely on the user's previous authentication information and user behavior which can be embedded with additional authentication methods according to the organization's requirements. In AMS, the administrator has the ability to add the appropriate authentication method based on the requirements of the organization. Based on these requirements, the administrator will activate and initialize the authentication method that has been added to the authentication pool. An intrusion detection component has been added to apply the users' location and users' default web browser feature. The AMS and intrusion detection components provide a security enhancement to increase the accuracy and efficiency of cloud user identity verification.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.479-482
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• 1998

Whether a given tree is a subgraph of the interconnection network topology is one of the important problem in parallel computing. Trees are used as the underlying structure for divide and conquer algorithms and provide the solution spaces for NP-complete problems. Complete binary trees are the basic structure among those trees. Binomial trees play an important role in broadcasting messages in parallel networks. If binomial trees can be efficiently embedded in complex binary trees, broadcasting algorithms can be effeciently performed on the interconnection networks. In this paper, we present average dilation 2 embedding of binomial trees in complete binary trees.

• 한국전산유체공학회:학술대회논문집
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• 2006.10a
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• pp.210-210
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• 2006

IT technologies(Chips, Grid and e-Science) are rapidly changed from 1965. In 1965, Intel co-founder Gordon Mooresaq the future. His prediction popularly known as Moore's law, state that the computer chips double in power every 18 months Grid computing offers a model for solving massive computational problems by making use of the unused resources of large numbers of disparate, often desktop, computers treated as a virtual cluster embedded in a distributed telecommunications infrastructure. In this paper, I will discuss current status of supercomputing technology and haw we can use these on CFD. Functionally, one can classify Grids into several types: