• Journal of Power Electronics
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• v.18 no.4
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• pp.1037-1050
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• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

• Journal of the Korea Computer Industry Society
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• v.4 no.10
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• pp.761-767
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• 2003

In this paper, A Fast Multi-level Successive Elimination Algorithm (FMSEA) is presented for block matching motion estimation in video coding. Motion estimation accuracy of FMSEA is equal to that of Multilevel Successive Elimination Algorithm(MSEA). FMSEA can reduce the computations for motion estimation of MSEA by using partial distortion elimination technique. The efficiency of the proposed algorithm was verified by experimental results.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.6 no.1
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• pp.40-48
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• 1992

In this paper, th technique of particular harmonics elimination in three-phase PWM Inverter is discussed. And voltage control technique is derived whereby harmonics elimination is possible in variable voltage variable frequency three-phase I.M.. The required switching patterns are determined on Personal Computer and the results are stored in look-up table in EPROM for controlling the switching of the PWM Inverter. The results show that experiments are in good agreement with simulation based on the theory.

• Journal of Electrical Engineering and Technology
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• v.6 no.3
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• pp.334-341
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• 2011

This paper presents accurate solutions for nonlinear transcendental equations of the selective harmonic elimination technique used in three-phase PWM inverters feeding the induction motor by particle swarm optimization (PSO). With the proposed approach, the required switching angles are computed efficiently to eliminate low order harmonics up to the $23^{rd}$ from the inverter voltage waveform, whereas the magnitude of the fundamental component is controlled to the desired value. A set of solutions and the evaluation of the proposed method are presented. The obtained results prove that the algorithm converges to a precise solution after several iterations. The salient contribution of the paper is the application of the particle swarm algorithm to attenuate successfully any undesired loworder harmonics from the inverter output voltage. The current paper demonstrates that the PSO is a promising approach to control the operation of a three-phase voltage source inverter with a selective harmonic elimination strategy to be applied in induction motor drives.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1682-1691
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• 2015

In this paper, a real time implementation of selective harmonic elimination pulse width modulation (SHEPWM) using Real Coded Genetic Algorithm (RGA), Particle Swarm Optimization technique (PSO) and a new technique known as Linearization Method (LM) for Single Phase Matrix Converter (SPMC) is designed and discussed. In the proposed technique, the switching frequency is fixed and the optimum switching angles are obtained using simple mathematical calculations. A MATLAB simulation was carried out, and FFT analysis of the simulated output voltage waveform confirms the effectiveness of the proposed method. An experimental setup was also developed, and the switching angles and firing pulses are generated using Field Programmable Gate Array (FPGA) processor. The proposed method proves that it is much applicable in the industrial applications by virtue of its suitability in real time applications.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.2
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• pp.185-190
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• 2010

This paper presents the estimation on switching technique via output power source analysis of power conversion unit in electric railway vehicle. The focus of this study suggested an alternative on critical problems by using head electric power(HEP). To achieve this, we have measured output power of HEP, and measurement devices set up at output of transformer connected HEP to analysis quality on output power source of head electric power(HEP) unit in electric railway vehicle. Using results of measurement of it, parameters are assumed for simulation to confirm estimation on switching technique. It is confirmed that switching technique is Selected Harmonic Elimination PWM(SHEPWM) and inverter switching frequency is less than 500[Hz]. Throughout experiment and simulation, it is estimated that switching technique used HEP is advanced SHEPWM and switching frequency is about 300[Hz]. Also leakage inductance in transformer is about $180[{\mu}H]$ less than $365[{\mu}H]$ known.

• The KIPS Transactions:PartA
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• v.18A no.3
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• pp.109-114
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• 2011

We describe a technique for automatically proving compiler optimizations sound, meaning that their transformations are always semantics-preserving. As is well known, IR (Intermediate Representation) optimization is an important step in a compiler backend. But unfortunately, it is difficult to detect and debug the IR optimization errors for compiler developers. So, we introduce a C level error check system for detecting the correctness of these IR transformation techniques. In our system, we first create an IR-to-C converter to translate IR to C code before and after each compiler optimization phase, respectively, since our technique is based on the Memory Comparison-based Clone(MeCC) detector which is a tool of detecting semantic equivalency in C level. MeCC accepts only C codes as its input and it uses a path-sensitive semantic-based static analyzer to estimate the memory states at exit point of each procedure, and compares memory states to determine whether the procedures are equal or not. But MeCC cannot guarantee two semantic-equivalency codes always have 100% similarity or two codes with different semantics does not get the result of 100% similarity. To increase the reliability of the results, we describe a technique which comprises how to generate C codes in IR-to-C transformation phase and how to send the optimization information to MeCC to avoid the occurrence of these unexpected problems. Our methodology is illustrated by three familiar optimizations, dead code elimination, instruction scheduling and common sub-expression elimination and our experimental results show that the C level error check system is highly reliable.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.944-951
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• 2015

Pulse Width Modulation (PWM) techniques are increasingly employed for PWM inverter fed induction motor drive. Among various popular PWM methods used, Selective Harmonic Elimination PWM (SHEPWM) has been widely accepted for its better harmonic elimination capability. In addition, using SHEPWM, it is also possible to maintain better voltage regulation. Hence, in this paper, an attempt has been made to apply Bacterial Foraging Algorithm (BFA) for solving selective harmonic elimination problem. The problem of voltage harmonic elimination together with output voltage regulation is drafted as an optimization task and the solution is sought through proposed method. For performance comparison of BFA, the results obtained are compared with other techniques such as derivative based Newton-Raphson method, and Genetic Algorithm. From the comparison, it can be observed that BFA based approach yields better results. Further, it provides superior convergence, reduced computational burden, and guaranteed global optima. The simulation results are validated through experimental findings.

• Journal of Power Electronics
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• v.17 no.4
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• pp.933-941
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• 2017

In this paper an improved low frequency selective harmonic elimination-PWM (SHE-PWM) technique for Cascaded H-bridge (CHB) converters is proposed. The proposed method is able to eliminate low order harmonics from the output voltage of the converter for a wide range of modulation indices. To solve SHE-PWM equations, especially for low modulation indices, a modified method is used which employs either the positive or negative voltage polarities of H-bridge cells to increase the freedom degrees of each cell. Freedom degrees of the switching angles are also used to increase the range of available solutions for non-linear SHE equations. The proposed SHE methods can successfully eliminate up to $25^{th}$ harmonic from a 7-level output voltage by using just nine switching transitions or a 150 Hz switching frequency. To confirm the validity of the proposed method, simulation and experimental results have been presented.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.4
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• pp.100-108
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• 1997

A combined buck and boost push-pull quantum series resonant rectifier(PPQSRR) is newly proposed to achieve a power factor correction without start-up inrush current. Based on the developed dynamic modeling of the proposed rectifier, an inrush current elimination control technique is proposed and the usefullness of the proposed rectifier and control method are verified by computer simulation and experimental results. With the proposed control method, a high power factor and wide range of output voltage can be obtained.