• 마이크로전자및패키징학회지
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• 제15권2호
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• pp.29-36
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• 2008

본 연구에서는 MEMS 소자의 직접화 및 소형화에 필수적인 through-wafer via interconnect의 신뢰성 문제를 연구하였다. 이를 위하여 Au-Sn eutectic 접합 기술을 이용하여 밀봉(hermetic) 접합을 한 웨이퍼 레벨 MEMS 패키지 소자를 개발하였으며, 전기도금법을 이용하여 수직 through-hole via 내부를 구리로 충전함으로써 전기적 연결을 시도하였다. 제작된 MEMS 패키지의 크기는 $1mm{\times}1mm{\times}700{\mu}m$이었다. 제작된 MEMS패키지의 신뢰성 수행 결과 비아 홀(via hole)주변의 크랙 발생으로 패키지의 파손이 발생하였다. 구리 through-via의 기계적 신뢰성에 영향을 줄 수 있는 여러 인자들에 대해서 수치적 해석 및 실험적인 연구를 수행하였다. 분석 결과 via hole의 크랙을 발생시킬 수 있는 파괴 인자로서 열팽창 계수의 차이, 비아 홀의 형상, 구리 확산 현상 등이 있었다. 궁극적으로 구리 확산을 방지하고, 전기도금 공정의 접합력을 향상시킬 수 있는 새로운 공정 방식을 적용함으로써 비아 홀 크랙으로 인한 패키지의 파괴를 개선할 수 있었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 International Symposium
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• pp.219-225
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• 2002

This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.49-53
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• 2002

The Sn-Cu eutectic solder bump formation ($140{\mu}{\textrm}{m}$ diameter, $250{\mu}{\textrm}{m}$ pitch) by electroplating was studied for flip chip package fabrication. The effect of current density and plating time on Sn-Cu deposit was investigated. The morphology and composition of plated solder surface was examined by scanning electron microscopy. The plating thickness increased with increasing time. The plating rate increased generally according to current density. After the characteristics of Sn-Cu plating were investigated, Sn-Cu solder bumps were fabricated on optimal condition of 5A/dm$^2$, 2hrs. Ball shear test after reflow was performed to measure adhesion strength between solder bump and UBM (Under Bump Metallization). The shear strength of Sn-Cu bump after reflow was higher than that of before reflow.

• 한국표면공학회지
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• 제8권2호
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• pp.1-6
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• 1975

A novel electroplating process is described and effects of anode lay-out thickness distribution and on platiting rate are discussed. Microphotograhic analysis indicates are compact and less "POROUS " than of barrel and rack. With this process production cost reduction and capacity increase could be achieved by a rate of 60% and 97% respectively, as compared to our present barrel plating process. This process disclose a number of beneficial processes such as color coding system on TO-92 package and development of a new tin bath formula.

• 한국표면공학회지
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• 제54권3호
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• pp.158-163
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• 2021

Some studies on electrochemical additive manufacturing of metals were summarized in this technical report, and development status of selective electrochemical 3D printing technology was introduced. In order to apply it to the PCB mass production process, essential considerations how to overcome the fundamental problems, such as the sizing, process sequence and PCB process design have been described.

• 마이크로전자및패키징학회지
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• 제13권4호
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• pp.57-63
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• 2006

칩 스택 패키지의 삼차원 interconnection에 적용을 위해 폭 $75{\sim}10\;{\mu}m$, 길이 3mm의 트랜치 비아에 대해 전기도금전류밀도 및 전류모드에 따른 Cu filling 특성을 분석하였다. 직류모드로 $1.25mA/cm^{2}$에서 Cu filling한 경우, 트랜치 비아의 폭이 $75{\sim}35{\mu}m$ 범위에서는 95% 이상의 높은 Cu filling ratio를 나타내었다. 직류 전류밀도 $2.5mA/cm^{2}$에서 Cu filling한 경우에는 $1.25mA/cm^{2}$ 조건에 비해 열등한 Cu filling ratio를 나타내었으며, 직류모드에 비해 펄스모드가 우수한 Cu filling 특성을 나타내었다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.25.1-25.1
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• 2011

Over the past few decades, metallic nanoparticles (NPs) have been of great interest due to their unique mesoscopic properties which distinguish them from those of bulk metals; such as lowered melting points, greater versatility that allows for more ease of processability, and tunable optical and mechanical properties. Due to these unique properties, potential opportunities are seen for applications that incorporate nanomaterials into optical and electronic devices. Specifically, the development of metallic NPs has gained significant interest within the electronics field and technological community as a whole. In this study, gold (Au) pads for surface finish in electronic package were developed by inkjet printing of Au NPs. The microstructures of inkjet-printed Au film were investigated by various thermal treatment conditions. The film showed the grain growth as well as bonding between NPs. The film became denser with pore elimination when NPs were sintered under gas flows of $N_2$-bubbled through formic acid ($FA/N_2$) and $N_2$, which resulted in improvement of electrical conductance. The resistivity of film was 4.79 ${\mu}{\Omega}$-cm, about twice of bulk value. From organic anlayses of FTIR, Raman spectroscopy, and TGA, the amount of organic residue in the film was 0.43% which meant considerable removal of the solvent or organic capping molecules. The solder ball shear test was adopted for solderability and shear strength value was 820 gf (1 gf=9.81 mN) on average. This shear strength is good enough to substitute the inkjet-printed Au nanoparticulate film for electroplating in electronic package.

• 마이크로전자및패키징학회지
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• 제12권2호
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• pp.111-119
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• 2005

직경 $75{\mu}m$ 높이 $90{\mu}m$및 $150{\mu}m$ 피치의 Cu via를 통한 삼차원 배선구조를 갖는 스택 시편을 deep RIE를 이용한 via hole 형성공정 , 펄스-역펄스 전기도금법에 의한 Cu via filling 공정, CMP를 이용한 Si thinning 공정, photholithography, 금속박막 스퍼터링, 전기도금법에 의한 Cu/Sn 범프 형성공정 및 플립칩 공정을 이용하여 제작하였다. Cu via를 갖는 daisy chain 시편에서 측정한 접속범프 개수에 따른 daisy chain의 저항 그래프의 기울기로부터 Cu/Sn 범프 접속저항과 Cu via 저항을 구하는 것이 가능하였다. $270^{\circ}C$에서 2분간 유지하여 플립칩 본딩시 $100{\times}100{\mu}m$크기의 Cu/Sn 범프 접속저항은 6.7 m$\Omega$이었으며, 직경 $75 {\mu}m$, 높이 $90{\mu}m$인 Cu via의 저항은 2.3m$\Omega$이었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• 센서학회지
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• 제20권1호
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• pp.58-63
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• 2011

A low loss radio frequency(RF) micro electro mechanical systems(MEMS) switch driven by a low actuation voltage was designed for the development of a new RF MEMS switch. The RF MEMS switch should be encapsulated. The glass cap and fabricated RF MEMS switch were assembled by the Au/Sn eutectic bonding principle for wafer-level packaging. The through-vias on the glass substrate was made by the glass dry etching and Au electroplating process. The packaged RF MEMS switch had an actuation voltage of 12.5 V, an insertion loss below 0.25 dB, a return loss above 16.6 dB, and an isolation value above 41.4 dB at 6 GHz.