• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.423-426
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• 1998

Piezoresistive pressure sensors have fabricated using electrochemical etch-stop technique. Si diaphragm having thickness of n-epi. layer was fabricated and used to detect pressure range from 0 to 1 kg/$\textrm{cm}^2$. Piezoresistors were diffused 3${\times}$10$\^$18/ cm$\^$-3/ and placed at diaphragm edge for maximum pressure detection. The characteristics of electrochemical etch-stop in TMAH/lPA/pyrazine solution were also discussed. I-V curves of n and p-type Si in TMAH/lPA/pyrazine solution were obtained. Etching rate is highest at optimum etching condition, TMAH 25wt.%/IPA 17vo1.%/pyrazine 0.1/100m1, thus the elapsed time of etch-stop was reduced.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.579-582
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• 2000

This paper described on the fabrication of SOI(Si-on-insulator) structures with buried cavities by SDB technology and eletrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annaling(100$0^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated the SDB SOI structure with buried cavities as well as an accurate control and a good flatness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.741-744
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• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1890-1892
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• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -750 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.301-306
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method, and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point, the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.397-400
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• 1997

This paper presentes the characteristics of Si anisotropic etching and electrochemical etch-stop in aqueous TMAH/IPA/pyrazine solution. (100) Si etching rate of 0.747 $\mu\textrm{m}$/min which faster 86% than TMAH 25 wt.%/IPA 17 vol.% solution was obtained using best etching condition at TMAH 25 wt.%/IPA 17 vol.%/pyrazine 0.1 g and the etching rate of (100) Si was decreased with more additive quantity of pyrazine. I-V curve of p-type Si in TMAH/IPA/pyrazine was obtained. OCP(Open Circuit Potential) and PP(Passivation Potential) were -2 V and -0.9 V, respectively. Si diaphragms were obtained by electrochemical etch-stop in aqueous TMAH/IPA/pyrazine solution.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.362-365
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• 1999

This paper describes on thinning SDB SOI substrates by SDB technology and electrochemical etch-stop. The surface of the fabricated SDB SOI substrates is more uniform than that grinding or polishing by mechanical method, and this process is possible to accurate SOI thickness control. During Electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential (OCP) point and the passivation potential (PP) poin and determinated to anodic substrates were analyzed by using AFM and SEM, respectivelv.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1369-1371
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• 2001

This paper describes on thinning SDB SOI substrates by SDB technology and Electro-chemical etch-stop. The surface of the fabricated SDB SOI substrates is more uniform than that grinding or polishing by mechanical method, and this process is possible to accurate SOI thickness control. During Electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential (OCP) point and the passivation potential (PP) poin and determinated to anodic passivation potential. The surface roughness and selectively controlled thickness of the fabricated SOI substrates were analyzed by using AFM and SEM, respectively.

• Journal of Sensor Science and Technology
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• v.11 no.1
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• pp.54-59
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• 2002

This paper describes a new process technique for batch process of SOI(Si-on-Insulator) structures with buried cavities for MEMS(Micro Electro Mechanical System) applications by SDB(Si-wafer Direct Bonding) technology and electrochemical etch-stop. A low-cost electrochemical etch-stop method is used to control accurately the thickness of SOI. The cavities were made on the upper handling wafer by Si anisotropic etching. Two wafers are bonded with an intermediate insulating oxide layer. After high-temperature annealing($1000^{\circ}C$, 60 min), the SDB SOI structure with buried cavities was thinned by electrochemical etch-stop. The surface of the fabricated SDB SOI structure have more roughness that of lapping and polishing by mechanical method. This SDB SOI structure with buried cavities will provide a powerful and versatile substrate for novel microsensors arid microactuators.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.739-742
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• 2002

This paper described on the fabrication of microstructures by DRIE(deep reactive ion etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing($1000^{\circ}C$, 60 min.), The SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as an accurate thickness control and a good flatness.